微處理器 - Lattice LCMXO2-4000HC-4MG132C (STEP-MXO2 V2) - VHDL - LED

參考資訊：
https://www.stepfpga.com/doc/step-mxo2%E5%85%A5%E9%97%A8%E6%95%99%E7%A8%8B

main.vhd

library ieee;
use ieee.std_logic_1164.all;
    
entity main is
    port(
        clk : in std_logic;
        led : out std_logic_vector(0 to 7) := "11111111"
    );
end main;
    
architecture logic of main is
begin
    process(clk) is
        variable cnt : integer := 0;
        variable val: std_logic_vector(0 to 7) := "11111111";
    begin
        if (clk'event and clk = '1') then
            cnt := cnt + 1;
  
            if (cnt = 1000000) then
                cnt := 0;
                led <= val;
                val := not val;
            end if;
        end if;
    end process;
end logic;

main.lpf

LOCATE COMP "led[0]" SITE "N13";
LOCATE COMP "led[1]" SITE "M12";
LOCATE COMP "led[2]" SITE "P12";
LOCATE COMP "led[3]" SITE "M11";
LOCATE COMP "led[4]" SITE "P11";
LOCATE COMP "led[5]" SITE "N10";
LOCATE COMP "led[6]" SITE "N9";
LOCATE COMP "led[7]" SITE "P9";
LOCATE COMP "clk" SITE "C1";

Makefile

all:
	yosys -m ghdl -p "ghdl main.vhd -e main; synth_lattice -family xo2 -json main.json"
	nextpnr-machxo2 --device LCMXO2-4000HC-4MG132C --lpf main.lpf --json main.json --textcfg main.txt
	ecppack --compress main.txt main.bit --jed main.jed

ram:
	openFPGALoader -b step-mxo2_v2 main.bit

flash:
	openFPGALoader -b step-mxo2_v2 main.jed

clean:
	rm -rf main.txt main.bit main.json main.jed

編譯、下載

$ make
$ make ram

完成