#+title: RISC-V 大杂烩
#+date: <2023-01-18 Wed 10:02>
#+author: thebesttv

曾经雄心勃勃想学RISC-V, 然后研究生学了其他的 = =

这里是之前记录RISC-V各种资源的笔记.

- [[https://ysyx.oscc.cc/][一生一芯计划 - 从零开始创造属于你的RISC-V处理器]]

* Roadmap

曾经的总目标: 从零开始用Verilog实现一个可以运行Linux的CPU
- Verilog
- 最简单,支持RV32I的CPU
- 添加流水线
- 添加特权模式
- MMU啥的

* 板子

- 哪吒
- LicheeRV D1
- [[https://www.iceasy.com/3261/1022722251.shtml][VisionFive]]

** 单片机

- ESP32C3
- 沁恒有不少更便宜的

* ASM

- [[https://passlab.github.io/ITSC3181/resources/RISC-VAssemblyProgramming.html][RISC-V Assembly Programming]]
- [[https://www.youtube.com/watch?v=bEUMLh2lasE][Learn Risc-V Assembly Programming - Lesson1 : For absolute beginners!]]

* Verilog

- [[https://www.amazon.com/dp/0983497303][Verilog by Example: A Concise Introduction for FPGA Design]]
- [[http://www.asic-world.com/verilog/index.html][ASIC-world Verilog page]]
- [[https://hdlbits.01xz.net/wiki/Main_Page][HDLBits---Verilog Practice]]

* 杂七杂八

- [[https://shakti.org.in/docs/risc-v-asm-manual.pdf][RISC-V ASSEMBLY LANGUAGE Programmer Manual Part I]] 看起来不错的汇编教程
- [[https://www.arch.cs.titech.ac.jp/wk/rvcore/doku.php][RVCore Project, Arch Lab, Tokyo Tech]]
- [[https://www.arch.cs.titech.ac.jp/wk/rvsoc/doku.php][RVSoC Project, a portable and Linux capable RISC-V computer system
  on an FPGA]]

- [[https://book.douban.com/subject/25960657/][自己动手写CPU]]: 从易到难实现了一个 MIPS CPU,感觉是本不错的书,但是MIPS
  架构,不会优先考虑

  看了一半评价: 代码风格比较糟糕... 不过确实让我入门了一下Verilog = =
  - [[https://github.com/zach0zhang/Single_instruction_cycle_OpenMIPS][Single instruction cycle OpenMIPS]]: 通过学习《自己动手写CPU》,将书
    中实现的兼容MIPS32指令集架构的处理器——OpenMIPS(五级流水线结构),
    简化成单指令周期实现的处理器
- [[https://book.douban.com/subject/25780703/][CPU自制入门]]: 可能和上一本类似,但上一本优先考虑

- [[https://github.com/juiceRv/JuiceVm][JuiceVm]] 可以在 ESP32 上跑的Linux虚拟机, 我震惊

[[https://opencores.org/][OpenCores]]: The reference community for Free and Open Source gateware
IP cores

[[https://club.rt-thread.org/ask/article/2327.html][在 Picorv32 / 蜂鸟 E203 软核上运行 RT-Thread]]: 用荔枝糖跑蜂鸟

[[https://github.com/riscvarchive/educational-materials][Educational materials for RISC-V]]: archived

[[https://www.chisel-lang.org/][Chisel/FIRRTL Hardware Compiler Framework]]: 可以用来实现 RISC-V 核的语言

[[https://github.com/BrunoLevy/learn-fpga][Learning FPGA, yosys, nextpnr, and RISC-V]]: 或许可以拿来学FPGA, 包括了
多个1k行以内的RISC-V核,最小的只有400行

[[https://diveintosystems.org][Dive Into Systems]]: 组原的开源教材

[[https://github.com/lmxyy/Computer-Architecture-Task-2][Lmxyy - Computer Architecture Task 2]]: Implement a Risc-v CPU using
hardware description language(HDL), and then download the CPU on FPGA.
Using C++ to simulate the memory via the USB-UART protocol.

[[https://domipheus.com/blog/post/][Domipheus Labs --- Designing a RISC-V CPU in VHDL]]

[[https://twitter.com/sylefeb/status/1507104033902837766][ICEBreaker上跑的双核RISC-V]]

[[https://f4pga-examples.readthedocs.io/en/latest/][F4PGA - open source FPGA toolchain]]

[[https://www.reddit.com/r/RISCV/comments/ues63l/first_project_%CE%BClisp_repl_over_serial/][First Project: μLisp REPL over serial?]]

* OpenMIPS

- [[https://github.com/GundamBox/DIY_OpenMIPS][DIY OPenMIPS]]: 比较可贵的事每篇都有实作心得 (虽然只到Ch9)

* Core

- UltraEmbedded 的三个核,从易到难
  - [[https://github.com/ultraembedded/core_uriscv][uriscv - Another tiny RISC-V implementation]]
  - [[https://github.com/ultraembedded/riscv][RISC-V Core]]
  - [[https://github.com/ultraembedded/biriscv][biRISC-V - 32-bit dual issue RISC-V CPU]]
- [[https://github.com/riscvarchive/riscv-cores-list][List of RISC-V Cores]]: archived
- [[https://github.com/OSCPU/NutShell][果壳]]: 感觉doc不是很全面
- [[https://github.com/openhwgroup/cva6][The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux]]
  - [[https://sazczmh.github.io/sazc-tech-notes/cva6-analysis-notes/cva6-jia-gou-gai-shu/][cva6架构概述]]
  - [[http://parallel.princeton.edu/openpiton/][OpenPiton]]: An Open Source Manycore Research Framework, 不知道是啥玩意
- [[https://github.com/SpinalHDL/VexRiscv][VexRiscV --- A FPGA friendly 32 bit RISC-V CPU implementation]]
- [[https://boom-core.org/][RISC-V BOOM --- The Berkeley Out-of-Order RISC-V Processor]]: 是
  out-of-order 的,感觉太高端了
- [[https://github.com/OpenXiangShan/XiangShan][香山 --- 高性能开源RISC-V处理器]]: 太高端了
- [[https://github.com/darklife/darkriscv][DarkRISCV --- opensouce RISC-V cpu core implemented in Verilog from
  scratch in one night!]]: 感觉不是很靠谱,不如蜂鸟
- [[https://github.com/PeterAaser/RISCV-FiveStage][RISCV-FiveStage]]: Chisel
- [[https://github.com/ucb-bar/riscv-mini][Simple RISC-V 3-stage Pipeline in Chisel]]
- [[https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/README.md][FemtoRV]]
- [[https://github.com/liangkangnan/tinyriscv][tinyriscv]]
  [[https://liangkangnan.gitee.io/2020/04/29/%E4%BB%8E%E9%9B%B6%E5%BC%80%E5%A7%8B%E5%86%99RISC-V%E5%A4%84%E7%90%86%E5%99%A8/][《从零开始写RISC-V处理器》]] 的配套代码

* Chisel

- [[https://github.com/freechipsproject/chisel-bootcamp][chisel-bootcamp]]: chisel 教程
- [[https://news.ycombinator.com/item?id=19010109][一些链接]]

* OS

- [[https://github.com/chyyuu/os_kernel_lab][OS kernel labs based on Rust/C Lang & RISC-V 64/X86-32]]: 从零开始用
  Rust 语言写一个基于 RISC-V 架构的 类 Unix 内核
- [[https://github.com/mit-pdos/xv6-riscv][Xv6 for RISC-V]]

* Simulator

- [[https://github.com/mortbopet/Ripes][Ripes]] A graphical processor simulator and assembly editor for the RISC-V ISA