(kicad_pcb
	(version 20260206)
	(generator "pcbnew")
	(generator_version "10.0")
	(general
		(thickness 1.6)
		(legacy_teardrops no)
	)
	(paper "A4")
	(title_block
		(rev "0.1.2")
	)
	(layers
		(0 "F.Cu" signal)
		(2 "B.Cu" signal)
		(9 "F.Adhes" user "F.Adhesive")
		(11 "B.Adhes" user "B.Adhesive")
		(13 "F.Paste" user)
		(15 "B.Paste" user)
		(5 "F.SilkS" user "F.Silkscreen")
		(7 "B.SilkS" user "B.Silkscreen")
		(1 "F.Mask" user)
		(3 "B.Mask" user)
		(17 "Dwgs.User" user "User.Drawings")
		(19 "Cmts.User" user "User.Comments")
		(21 "Eco1.User" user "User.Eco1")
		(23 "Eco2.User" user "User.Eco2")
		(25 "Edge.Cuts" user)
		(27 "Margin" user)
		(31 "F.CrtYd" user "F.Courtyard")
		(29 "B.CrtYd" user "B.Courtyard")
		(35 "F.Fab" user)
		(33 "B.Fab" user)
		(39 "User.1" user)
		(41 "User.2" user)
		(43 "User.3" user)
		(45 "User.4" user)
	)
	(setup
		(stackup
			(layer "F.SilkS"
				(type "Top Silk Screen")
				(color "White")
			)
			(layer "F.Paste"
				(type "Top Solder Paste")
			)
			(layer "F.Mask"
				(type "Top Solder Mask")
				(color "Black")
				(thickness 0.01)
			)
			(layer "F.Cu"
				(type "copper")
				(thickness 0.035)
			)
			(layer "dielectric 1"
				(type "core")
				(thickness 1.51)
				(material "FR4")
				(epsilon_r 4.5)
				(loss_tangent 0.02)
			)
			(layer "B.Cu"
				(type "copper")
				(thickness 0.035)
			)
			(layer "B.Mask"
				(type "Bottom Solder Mask")
				(color "Black")
				(thickness 0.01)
			)
			(layer "B.Paste"
				(type "Bottom Solder Paste")
			)
			(layer "B.SilkS"
				(type "Bottom Silk Screen")
				(color "White")
			)
			(copper_finish "ENIG")
			(dielectric_constraints no)
		)
		(pad_to_mask_clearance 0.0762)
		(allow_soldermask_bridges_in_footprints no)
		(tenting
			(front yes)
			(back yes)
		)
		(covering
			(front no)
			(back no)
		)
		(plugging
			(front no)
			(back no)
		)
		(capping no)
		(filling no)
		(pcbplotparams
			(layerselection 0x00000000_00000000_55555555_5755f5ff)
			(plot_on_all_layers_selection 0x00000000_00000000_00000000_00000000)
			(disableapertmacros no)
			(usegerberextensions no)
			(usegerberattributes yes)
			(usegerberadvancedattributes yes)
			(creategerberjobfile yes)
			(dashed_line_dash_ratio 12)
			(dashed_line_gap_ratio 3)
			(svgprecision 4)
			(plotframeref no)
			(mode 1)
			(useauxorigin no)
			(pdf_front_fp_property_popups yes)
			(pdf_back_fp_property_popups yes)
			(pdf_metadata yes)
			(pdf_single_document no)
			(dxfpolygonmode yes)
			(dxfimperialunits yes)
			(dxfusepcbnewfont yes)
			(psnegative no)
			(psa4output no)
			(plot_black_and_white yes)
			(sketchpadsonfab no)
			(plotpadnumbers no)
			(hidednponfab no)
			(sketchdnponfab yes)
			(crossoutdnponfab yes)
			(subtractmaskfromsilk no)
			(outputformat 1)
			(mirror no)
			(drillshape 0)
			(scaleselection 1)
			(outputdirectory "Gerber")
		)
	)
	(footprint "FoveaCamDuo:JST_PH_S6B-PH-K_1x06_P2.00mm_Horizontal_NoSilkScreen"
		(layer "B.Cu")
		(uuid "00917375-5278-46a1-826d-9ca16eee31de")
		(at -14.304 14.75 180)
		(descr "JST PH series connector, S6B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator. Extracted verbatim (pads, graphics, 3D model reference) from the footprint embedded as J_CAM0 in the original hand-drawn FoveaCamDuo-PCB.kicad_pcb (KiCad 9, git 289fb6c); not in the stock KiCad 10 library. Original library id: Connector_JST:JST_PH_S6B-PH-K_1x06_P2.00mm_Horizontal_NoSilkScreen. Drill 2026-10-07 (owner, v0.1.2): 0.80 mm finished (0.75 before): JST ePH.pdf p1 gives the PCB hole as 0.7 +0.1/0 and note 3 asks for a larger hole on glass-fibre boards; at fab tolerance a 0.75 hole can finish at 0.67 (JLCPCB -0.08) or 0.623 (Advanced PCB -0.127), below JST's 0.7. Pads stay 1.2 x 1.75 mm: plated ring 0.20 mm (>= JLCPCB 0.18, Advanced 0.178).")
		(tags "connector JST PH horizontal")
		(property "Reference" "J_CAM1"
			(at 5 2.55 0)
			(layer "B.SilkS")
			(hide yes)
			(uuid "ba23cef3-6c3f-41dc-88db-9120ae8f0635")
			(effects
				(font
					(size 1 1)
					(thickness 0.15)
				)
				(justify mirror)
			)
		)
		(property "Value" "Conn_01x06"
			(at 5 -7.45 0)
			(layer "B.Fab")
			(hide yes)
			(uuid "adb58c17-9646-4527-80f4-f73b3c8ef324")
			(effects
				(font
					(size 1 1)
					(thickness 0.15)
				)
				(justify mirror)
			)
		)
		(property "Datasheet" "~"
			(at 0 0 0)
			(layer "B.Fab")
			(hide yes)
			(uuid "f83a7e03-d58b-4d0a-8d5b-c1c8c2de7f50")
			(effects
				(font
					(size 1.27 1.27)
					(thickness 0.15)
				)
				(justify mirror)
			)
		)
		(property "Description" "Generic connector, single row, 01x06, script generated (kicad-library-utils/schlib/autogen/connector/)"
			(at 0 0 0)
			(layer "B.Fab")
			(hide yes)
			(uuid "b519b45f-c2b0-49ea-8f73-076e7e3e75bb")
			(effects
				(font
					(size 1.27 1.27)
					(thickness 0.15)
				)
				(justify mirror)
			)
		)
		(property "Manufacturer" "JST"
			(at 0 0 0)
			(layer "B.Fab")
			(hide yes)
			(uuid "6d2b868e-ffd9-44cc-8b67-b7d9dbb3dd30")
			(effects
				(font
					(size 1.27 1.27)
					(thickness 0.15)
				)
				(justify mirror)
			)
		)
		(property "MPN" "S6B-PH-K-S"
			(at 0 0 0)
			(layer "B.Fab")
			(hide yes)
			(uuid "70538bdf-7b1c-41d3-80c5-71b31cf1b66d")
			(effects
				(font
					(size 1.27 1.27)
					(thickness 0.15)
				)
				(justify mirror)
			)
		)
		(property "Distributor PN" "Digi-Key 455-1723-ND"
			(at 0 0 0)
			(layer "B.Fab")
			(hide yes)
			(uuid "ff507659-659f-4c92-8faa-8cc252075c9b")
			(effects
				(font
					(size 1.27 1.27)
					(thickness 0.15)
				)
				(justify mirror)
			)
		)
		(property "Notes" "PH 2.0 mm 6-pin side entry, 4.80 mm high; mating face 6.25 mm from the pin row (JST ePH.pdf p1); plug PHR-6 + SPH-002T-P0.5S"
			(at 0 0 0)
			(layer "B.Fab")
			(hide yes)
			(uuid "6ef636a7-9b7b-4a36-8d95-9c91d04facaf")
			(effects
				(font
					(size 1.27 1.27)
					(thickness 0.15)
				)
				(justify mirror)
			)
		)
		(property ki_fp_filters "Connector*:*_1x??_*")
		(path "/2d303b24-4652-51d6-8ba5-7774561e4bba")
		(sheetname "/")
		(sheetfile "FoveaCamDuo-PCB.kicad_sch")
		(attr through_hole)
		(duplicate_pad_numbers_are_jumpers no)
		(fp_line
			(start 12.45 1.85)
			(end -2.45 1.85)
			(stroke
				(width 0.05)
				(type solid)
			)
			(layer "B.CrtYd")
			(uuid "c23e7675-ee1e-4d28-800c-452339ce1d68")
		)
		(fp_line
			(start 12.45 -6.75)
			(end 12.45 1.85)
			(stroke
				(width 0.05)
				(type solid)
			)
			(layer "B.CrtYd")
			(uuid "46523849-07e1-4d66-8b62-8eae7a48eacc")
		)
		(fp_line
			(start -2.45 1.85)
			(end -2.45 -6.75)
			(stroke
				(width 0.05)
				(type solid)
			)
			(layer "B.CrtYd")
			(uuid "e6c9fcd6-49a3-4a9f-8fe4-6b6ce27cf56f")
		)
		(fp_line
			(start -2.45 -6.75)
			(end 12.45 -6.75)
			(stroke
				(width 0.05)
				(type solid)
			)
			(layer "B.CrtYd")
			(uuid "06692436-3211-4699-8812-eb2b271451cf")
		)
		(fp_line
			(start 11.95 1.35)
			(end 11.25 1.35)
			(stroke
				(width 0.1)
				(type solid)
			)
			(layer "B.Fab")
			(uuid "bad638f5-2ce2-4536-87ec-2c97b937f283")
		)
		(fp_line
			(start 11.95 -6.25)
			(end 11.95 1.35)
			(stroke
				(width 0.1)
				(type solid)
			)
			(layer "B.Fab")
			(uuid "b868ba8c-9bfb-4174-8268-4c08d32b94e1")
		)
		(fp_line
			(start 11.25 1.35)
			(end 11.25 -0.25)
			(stroke
				(width 0.1)
				(type solid)
			)
			(layer "B.Fab")
			(uuid "4d3c3322-0d3c-44e6-8ab4-bbbe799247de")
		)
		(fp_line
			(start 11.25 -0.25)
			(end -1.25 -0.25)
			(stroke
				(width 0.1)
				(type solid)
			)
			(layer "B.Fab")
			(uuid "58b773e8-c2ea-4f1c-89f8-cd82c5af4dd8")
		)
		(fp_line
			(start 0.5 -1.375)
			(end 0 -0.875)
			(stroke
				(width 0.1)
				(type solid)
			)
			(layer "B.Fab")
			(uuid "e3b6a57e-9884-4361-8ccb-5d89c2a42c44")
		)
		(fp_line
			(start 0 -0.875)
			(end -0.5 -1.375)
			(stroke
				(width 0.1)
				(type solid)
			)
			(layer "B.Fab")
			(uuid "e0292aed-56b2-4f46-87d8-d8f0ece6841d")
		)
		(fp_line
			(start -0.5 -1.375)
			(end 0.5 -1.375)
			(stroke
				(width 0.1)
				(type solid)
			)
			(layer "B.Fab")
			(uuid "39cb3e20-68a9-4a71-859f-6b8883ee5f2f")
		)
		(fp_line
			(start -1.25 1.35)
			(end -1.95 1.35)
			(stroke
				(width 0.1)
				(type solid)
			)
			(layer "B.Fab")
			(uuid "bc7e20e4-cbc6-481a-842c-dcacbb384f3b")
		)
		(fp_line
			(start -1.25 -0.25)
			(end -1.25 1.35)
			(stroke
				(width 0.1)
				(type solid)
			)
			(layer "B.Fab")
			(uuid "da7b99e7-6ab0-4f86-8ba3-05dbfc404d9f")
		)
		(fp_line
			(start -1.95 1.35)
			(end -1.95 -6.25)
			(stroke
				(width 0.1)
				(type solid)
			)
			(layer "B.Fab")
			(uuid "6aae4a38-0273-4a17-80e6-7b0add4b2e54")
		)
		(fp_line
			(start -1.95 -6.25)
			(end 11.95 -6.25)
			(stroke
				(width 0.1)
				(type solid)
			)
			(layer "B.Fab")
			(uuid "5f777af2-f5bc-4aef-80a2-f099e6af24a4")
		)
		(pad "1" thru_hole roundrect
			(at 0 0 180)
			(size 1.2 1.75)
			(drill 0.8)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(roundrect_rratio 0.208333)
			(net "CAM1_L3")
			(pinfunction "Pin_1")
			(pintype "passive")
			(uuid "6e2c00f9-f076-4930-8ee1-5b51a88d6133")
		)
		(pad "2" thru_hole oval
			(at 2 0 180)
			(size 1.2 1.75)
			(drill 0.8)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "CAM1_IN")
			(pinfunction "Pin_2")
			(pintype "passive")
			(uuid "425cc844-bb06-4992-8a1a-520e51ef4c63")
		)
		(pad "3" thru_hole oval
			(at 4 0 180)
			(size 1.2 1.75)
			(drill 0.8)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "CAM1_L2")
			(pinfunction "Pin_3")
			(pintype "passive")
			(uuid "635d5f98-f60f-4368-87d1-3b11e6e491fc")
		)
		(pad "4" thru_hole oval
			(at 6 0 180)
			(size 1.2 1.75)
			(drill 0.8)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "CAM1_OUT")
			(pinfunction "Pin_4")
			(pintype "passive")
			(uuid "8290c0dc-7471-4aa7-8254-9245139b44e2")
		)
		(pad "5" thru_hole oval
			(at 8 0 180)
			(size 1.2 1.75)
			(drill 0.8)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "GND")
			(pinfunction "Pin_5")
			(pintype "passive")
			(uuid "f6a89858-5f1c-4b7b-80c0-a9686999ea18")
		)
		(pad "6" thru_hole oval
			(at 10 0 180)
			(size 1.2 1.75)
			(drill 0.8)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "GND")
			(pinfunction "Pin_6")
			(pintype "passive")
			(uuid "a3eaad3c-5911-4670-8d09-61613d7ed256")
		)
		(embedded_fonts no)
		(model "${KICAD9_3DMODEL_DIR}/Connector_JST.3dshapes/JST_PH_S6B-PH-K_1x06_P2.00mm_Horizontal.step"
			(offset
				(xyz 0 0 0)
			)
			(scale
				(xyz 1 1 1)
			)
			(rotate
				(xyz 0 0 0)
			)
		)
	)
	(footprint "FoveaCamDuo:JST_PH_S6B-PH-K_1x06_P2.00mm_Horizontal_NoSilkScreen"
		(layer "B.Cu")
		(uuid "0e0860b3-ebcc-49df-8b7c-77085760ceda")
		(at 24.304 14.75 180)
		(descr "JST PH series connector, S6B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator. Extracted verbatim (pads, graphics, 3D model reference) from the footprint embedded as J_CAM0 in the original hand-drawn FoveaCamDuo-PCB.kicad_pcb (KiCad 9, git 289fb6c); not in the stock KiCad 10 library. Original library id: Connector_JST:JST_PH_S6B-PH-K_1x06_P2.00mm_Horizontal_NoSilkScreen. Drill 2026-10-07 (owner, v0.1.2): 0.80 mm finished (0.75 before): JST ePH.pdf p1 gives the PCB hole as 0.7 +0.1/0 and note 3 asks for a larger hole on glass-fibre boards; at fab tolerance a 0.75 hole can finish at 0.67 (JLCPCB -0.08) or 0.623 (Advanced PCB -0.127), below JST's 0.7. Pads stay 1.2 x 1.75 mm: plated ring 0.20 mm (>= JLCPCB 0.18, Advanced 0.178).")
		(tags "connector JST PH horizontal")
		(property "Reference" "J_CAM2"
			(at 5 2.55 0)
			(layer "B.SilkS")
			(hide yes)
			(uuid "99472ad1-d2b6-45e8-815f-7f1f5bd57a4b")
			(effects
				(font
					(size 1 1)
					(thickness 0.15)
				)
				(justify mirror)
			)
		)
		(property "Value" "Conn_01x06"
			(at 5 -7.45 0)
			(layer "B.Fab")
			(hide yes)
			(uuid "bd081695-ee6c-4a4a-8fc2-878ae3c2f6ff")
			(effects
				(font
					(size 1 1)
					(thickness 0.15)
				)
				(justify mirror)
			)
		)
		(property "Datasheet" "~"
			(at 0 0 0)
			(layer "B.Fab")
			(hide yes)
			(uuid "fc3f3abe-6173-4b19-8a00-2f028b22baf0")
			(effects
				(font
					(size 1.27 1.27)
					(thickness 0.15)
				)
				(justify mirror)
			)
		)
		(property "Description" "Generic connector, single row, 01x06, script generated (kicad-library-utils/schlib/autogen/connector/)"
			(at 0 0 0)
			(layer "B.Fab")
			(hide yes)
			(uuid "3072dc4b-50dc-43be-836d-d31f16461215")
			(effects
				(font
					(size 1.27 1.27)
					(thickness 0.15)
				)
				(justify mirror)
			)
		)
		(property "Manufacturer" "JST"
			(at 0 0 0)
			(layer "B.Fab")
			(hide yes)
			(uuid "92548d9e-f0d5-4358-8368-46d1147dc242")
			(effects
				(font
					(size 1.27 1.27)
					(thickness 0.15)
				)
				(justify mirror)
			)
		)
		(property "MPN" "S6B-PH-K-S"
			(at 0 0 0)
			(layer "B.Fab")
			(hide yes)
			(uuid "e8d95750-3e54-40de-8e8d-4edeb36ac1e2")
			(effects
				(font
					(size 1.27 1.27)
					(thickness 0.15)
				)
				(justify mirror)
			)
		)
		(property "Distributor PN" "Digi-Key 455-1723-ND"
			(at 0 0 0)
			(layer "B.Fab")
			(hide yes)
			(uuid "6d317942-ecfc-4fa0-8e51-e976e4ac305e")
			(effects
				(font
					(size 1.27 1.27)
					(thickness 0.15)
				)
				(justify mirror)
			)
		)
		(property "Notes" "PH 2.0 mm 6-pin side entry, 4.80 mm high; mating face 6.25 mm from the pin row (JST ePH.pdf p1); plug PHR-6 + SPH-002T-P0.5S"
			(at 0 0 0)
			(layer "B.Fab")
			(hide yes)
			(uuid "c5c28049-03f2-409f-895c-737f400f5d51")
			(effects
				(font
					(size 1.27 1.27)
					(thickness 0.15)
				)
				(justify mirror)
			)
		)
		(property ki_fp_filters "Connector*:*_1x??_*")
		(path "/dca20c84-6722-5c77-b390-932db2265453")
		(sheetname "/")
		(sheetfile "FoveaCamDuo-PCB.kicad_sch")
		(attr through_hole)
		(duplicate_pad_numbers_are_jumpers no)
		(fp_line
			(start 12.45 1.85)
			(end -2.45 1.85)
			(stroke
				(width 0.05)
				(type solid)
			)
			(layer "B.CrtYd")
			(uuid "31a4816d-be2b-4810-8254-5068a50f562b")
		)
		(fp_line
			(start 12.45 -6.75)
			(end 12.45 1.85)
			(stroke
				(width 0.05)
				(type solid)
			)
			(layer "B.CrtYd")
			(uuid "8ca74fe1-5246-4821-8aed-d98092cb5e1e")
		)
		(fp_line
			(start -2.45 1.85)
			(end -2.45 -6.75)
			(stroke
				(width 0.05)
				(type solid)
			)
			(layer "B.CrtYd")
			(uuid "3ccbefd6-94fb-4bd5-8bf6-c83cf4c56ebf")
		)
		(fp_line
			(start -2.45 -6.75)
			(end 12.45 -6.75)
			(stroke
				(width 0.05)
				(type solid)
			)
			(layer "B.CrtYd")
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		(fp_text user "${REFERENCE}"
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	(footprint "FoveaCamDuo:MountingHole_2.7mm_M2.5_Pad5.0"
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			(uuid "19111235-a02d-424a-8690-d85cda092372")
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	(footprint "FoveaCamDuo:PinHeader_1x10_P1.27mm_Horizontal_Box"
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		(uuid "64a79767-26e1-48a9-80ba-4c0cc22a3eac")
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		(descr "Drill 0.68 mm finished (owner 2026-10-07: V0.0's 0.762 felt loose; CNC Tech allows 0.70 +/-0.05; pin SQ0.40 +/-0.02, diagonal <= 0.594; at JLCPCB -0.08 the hole is >= 0.60, at Advanced the order requests +/-0.003 in, >= 0.604); ring (1.06 - 0.68) / 2 = 0.19 mm. Body and courtyard 2026-10-07 from the current CNC Tech drawing 3220-XX-0200-00_.pdf (05-FEB-2020, https://www.cnctech.us/pdfs/3220-XX-0200-00_.pdf): housing 12.70 long, 4.90 deep, rear face 1.00 behind the near (even) row, so the mating face is 5.90 from it; drill 0.70 (recommended hole); silk outline dropped (the body sticks out of the board edge). Pad positions and 3D model reference extracted the footprint embedded as J_SPI1 in the original hand-drawn FoveaCamDuo-PCB.kicad_pcb (KiCad 9, git 289fb6c); not in the stock KiCad 10 library. Original library id: Connector_PinHeader_1.27mm:PinHeader_1x10_P1.27mm_Horizontal_Box. 3D model 2026-10-07: CNC Tech 3220-10-0200-00 manufacturer STEP, unmodified (https://www.cnctech.us/pdfs/3220-10-0200-00%203D.ZIP, linked from https://www.cnctech.us/productdetails.asp?ID=2227; matches the current drawing https://www.cnctech.us/pdfs/3220-XX-0200-00_.pdf, 05-FEB-2020: housing 12.70 x 4.90 deep x 5.0 high, rear face 0.80 to the near tail edge = 1.00 to the near row centre, mating face 5.90 from the near (even) row, tails 2.4, key slot in the wall away from the board). Pads 2026-10-07: 1.06 mm round (1.016 in v0.1.0, 1.07 earlier in v0.1.1): plated ring 0.18 mm, exactly JLCPCB's 2-layer 1 oz PTH minimum (fab review F4), and 0.21 mm copper space between pins >= the owner's 0.008 in (0.2032 mm) floor (owner 2026-10-07, \"Outer Min Space 0.008\"); with the 0.70 mm drill of the CNC Tech drawing a 1.27 mm grid allows at most 1.0668 mm (ring 0.183, space 0.2032), so the ring sits at the minimum by design. Solder mask 2026-10-07 (Advanced PCB standard spec, owner \"Use standard spec\"): one gang opening per face over all ten pads (filled rectangles on F.Mask / B.Mask, pad field + 0.0762 mm), no mask web between the pins: at 1.27 mm pitch the 0.20 mm copper gap cannot hold a web >= 0.1016 mm (Advanced) or 0.13 mm (JLCPCB black) once each pad keeps the 0.0762 mm mask clearance Advanced's standard spec needs; the pads use the board expansion; attribute allow_soldermask_bridges marks the gang opening as intended for KiCad DRC.")
		(tags "3220-10-0200-00 ")
		(property "Reference" "J_SPI2"
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			(layers "*.Cu" "*.Mask")
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			(remove_unused_layers no)
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			(net "SCLK2")
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			(net "FCLK")
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		(pad "10" thru_hole circle
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			(size 1.06 1.06)
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			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "FCLK")
			(pinfunction "FCLK_Y")
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			(uuid "aa343a40-0b9b-4a14-82bf-5731e14525e3")
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		(embedded_fonts no)
		(model "${KIPRJMOD}/../lib/3dmodels/FoveaCamDuo.3dshapes/CNCTech_3220-10-0200-00.step"
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	(footprint "FoveaCamDuo:JST_PH_S2B-PH-K_1x02_P2.00mm_Horizontal_NoSilkScreen"
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		(uuid "7d63265f-747b-4a21-8da2-2343cdd2344c")
		(at -27.75 9.25 90)
		(descr "JST PH series connector, S2B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf). KiCad 10 stock Connector_JST:JST_PH_S2B-PH-K_1x02_P2.00mm_Horizontal (kicad-footprint-generator, built from the JST drawing) with the silkscreen removed (FoveaCam Duo house style, as for the camera ports); fab, courtyard and 3D model unchanged. Added 2026-10-07 (owner: XH -> PH 2.0 mm). Drill 2026-10-07 (owner, v0.1.2): 0.80 mm finished (0.75 before): JST ePH.pdf p1 gives the PCB hole as 0.7 +0.1/0 and note 3 asks for a larger hole on glass-fibre boards; at fab tolerance a 0.75 hole can finish at 0.67 (JLCPCB -0.08) or 0.623 (Advanced PCB -0.127), below JST's 0.7. Pads stay 1.2 x 1.75 mm: plated ring 0.20 mm (>= JLCPCB 0.18, Advanced 0.178).")
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			(at 0 0 270)
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			(uuid "bc8ca64d-d304-4aa4-8111-afcc3a0ad5ef")
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		(property "Notes" "PH 2.0 mm 2-pin side entry; mating face 6.25 mm from the pin row, as the S6B-PH-K (JST ePH.pdf; KiCad stock land); fan output, pin 1 = +5V; plug PHR-2 + SPH-002T-P0.5S"
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		(path "/bef51ed0-32d3-5a3b-bac3-8924a023e55a")
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		(sheetfile "FoveaCamDuo-PCB.kicad_sch")
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			(uuid "520e72bc-c331-4187-8da3-b7dc234cc63f")
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			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(roundrect_rratio 0.208333)
			(net "+5V")
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			(pintype "passive")
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		(model "${KICAD10_3DMODEL_DIR}/Connector_JST.3dshapes/JST_PH_S2B-PH-K_1x02_P2.00mm_Horizontal.step"
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	(footprint "FoveaCamDuo:PinHeader_1x10_P1.27mm_Horizontal_Box"
		(layer "B.Cu")
		(uuid "7e51177b-46ae-4130-83e0-7b2a36bcd24b")
		(at -28.1 -9.652 -90)
		(descr "Drill 0.68 mm finished (owner 2026-10-07: V0.0's 0.762 felt loose; CNC Tech allows 0.70 +/-0.05; pin SQ0.40 +/-0.02, diagonal <= 0.594; at JLCPCB -0.08 the hole is >= 0.60, at Advanced the order requests +/-0.003 in, >= 0.604); ring (1.06 - 0.68) / 2 = 0.19 mm. Body and courtyard 2026-10-07 from the current CNC Tech drawing 3220-XX-0200-00_.pdf (05-FEB-2020, https://www.cnctech.us/pdfs/3220-XX-0200-00_.pdf): housing 12.70 long, 4.90 deep, rear face 1.00 behind the near (even) row, so the mating face is 5.90 from it; drill 0.70 (recommended hole); silk outline dropped (the body sticks out of the board edge). Pad positions and 3D model reference extracted the footprint embedded as J_SPI1 in the original hand-drawn FoveaCamDuo-PCB.kicad_pcb (KiCad 9, git 289fb6c); not in the stock KiCad 10 library. Original library id: Connector_PinHeader_1.27mm:PinHeader_1x10_P1.27mm_Horizontal_Box. 3D model 2026-10-07: CNC Tech 3220-10-0200-00 manufacturer STEP, unmodified (https://www.cnctech.us/pdfs/3220-10-0200-00%203D.ZIP, linked from https://www.cnctech.us/productdetails.asp?ID=2227; matches the current drawing https://www.cnctech.us/pdfs/3220-XX-0200-00_.pdf, 05-FEB-2020: housing 12.70 x 4.90 deep x 5.0 high, rear face 0.80 to the near tail edge = 1.00 to the near row centre, mating face 5.90 from the near (even) row, tails 2.4, key slot in the wall away from the board). Pads 2026-10-07: 1.06 mm round (1.016 in v0.1.0, 1.07 earlier in v0.1.1): plated ring 0.18 mm, exactly JLCPCB's 2-layer 1 oz PTH minimum (fab review F4), and 0.21 mm copper space between pins >= the owner's 0.008 in (0.2032 mm) floor (owner 2026-10-07, \"Outer Min Space 0.008\"); with the 0.70 mm drill of the CNC Tech drawing a 1.27 mm grid allows at most 1.0668 mm (ring 0.183, space 0.2032), so the ring sits at the minimum by design. Solder mask 2026-10-07 (Advanced PCB standard spec, owner \"Use standard spec\"): one gang opening per face over all ten pads (filled rectangles on F.Mask / B.Mask, pad field + 0.0762 mm), no mask web between the pins: at 1.27 mm pitch the 0.20 mm copper gap cannot hold a web >= 0.1016 mm (Advanced) or 0.13 mm (JLCPCB black) once each pad keeps the 0.0762 mm mask clearance Advanced's standard spec needs; the pads use the board expansion; attribute allow_soldermask_bridges marks the gang opening as intended for KiCad DRC.")
		(tags "3220-10-0200-00 ")
		(property "Reference" "J_SPI1"
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			(at 7.62 -11.43 270)
			(size 2 1.36)
			(drill 1)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "CAM2_OUT")
			(pinfunction "RX3")
			(pintype "bidirectional")
			(uuid "74e5bad2-df6f-46ef-8ad3-07fd5b9e1dba")
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		(pad "16" thru_hole oval
			(at 7.62 -8.89 270)
			(size 2 1.36)
			(drill 1)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "CAM0_L3")
			(pinfunction "RX4")
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			(uuid "b88a313e-3f4e-412a-8d80-42fbb0afd9ba")
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		(pad "17" thru_hole oval
			(at 7.62 -6.35 270)
			(size 2 1.36)
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			(net "CAM0_IN")
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			(uuid "ee2c3efb-fd6f-4505-8b22-195f8221ad8b")
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		(pad "18" thru_hole oval
			(at 7.62 -3.81 270)
			(size 2 1.36)
			(drill 1)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "CAM0_L2")
			(pinfunction "GPIO")
			(pintype "bidirectional")
			(uuid "9a0da6e0-d008-4d0e-8386-4db026161e6b")
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		(pad "19" thru_hole oval
			(at 7.62 -1.27 270)
			(size 2 1.36)
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			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "CAM0_OUT")
			(pinfunction "GPIO")
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			(uuid "00364a17-cae6-4eb1-8265-d9c2aac8df4c")
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		(pad "20" thru_hole oval
			(at 7.62 1.27 270)
			(size 2 1.36)
			(drill 1)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "CAM1_L3")
			(pinfunction "TX5")
			(pintype "bidirectional")
			(uuid "038e881b-bd29-454b-8d31-ceedbd53d51f")
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		(pad "21" thru_hole oval
			(at 7.62 3.81 270)
			(size 2 1.36)
			(drill 1)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "CAM1_IN")
			(pinfunction "RX5")
			(pintype "bidirectional")
			(uuid "5e2a803b-cf6e-451b-85f3-ada0fc7157d6")
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		(pad "22" thru_hole oval
			(at 7.62 6.35 270)
			(size 2 1.36)
			(drill 1)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "CAM1_L2")
			(pinfunction "GPIO")
			(pintype "bidirectional")
			(uuid "2727b6f3-8711-4a3e-8cfb-2c4783e31fc4")
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		(pad "23" thru_hole oval
			(at 7.62 8.89 270)
			(size 2 1.36)
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			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "CAM1_OUT")
			(pinfunction "GPIO")
			(pintype "bidirectional")
			(uuid "32a2ad8a-1a26-4709-8c7e-b937361d7bae")
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		(pad "24" thru_hole oval
			(at 7.62 11.43 270)
			(size 2 1.36)
			(drill 1)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "+3V3")
			(pinfunction "3V3")
			(pintype "power_out")
			(uuid "92995c65-daa9-4ea6-887a-59c9b470c0dc")
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		(pad "25" thru_hole oval
			(at 7.62 13.97 270)
			(size 2 1.36)
			(drill 1)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "GND")
			(pinfunction "GND")
			(pintype "bidirectional")
			(uuid "ed7457c1-8552-496c-8ec7-a54e5b56c731")
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		(pad "26" thru_hole oval
			(at 7.62 16.51 270)
			(size 2 1.36)
			(drill 1)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "+5V")
			(pinfunction "VIN")
			(pintype "power_out")
			(uuid "52fbaea7-52e5-4c0a-864c-9c20694f1ad2")
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		(pad "G" thru_hole roundrect
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			(size 2 1.36)
			(drill 1)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(roundrect_rratio 0.1406074241)
			(net "GND")
			(pinfunction "GND")
			(pintype "bidirectional")
			(uuid "ad820ecd-58ef-4aed-8046-85f9e64ff379")
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		(embedded_fonts no)
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	(footprint "FoveaCamDuo:MountingHole_2.7mm_M2.5_Pad5.0"
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		(uuid "93895f97-aa32-43d7-84a3-8eca7cf351d8")
		(at -30 -17)
		(descr "Plated mounting hole 2.7 mm (M2.5 clearance) with a 5.0 mm round pad on both faces, no net. KiCad 10 stock MountingHole:MountingHole_2.7mm_M2.5_Pad (kicad-footprint-generator) with the pad reduced from 5.4 to 5.0 mm and the courtyard to r 2.75, so the copper keeps 0.5 mm from the board's r 3 corner arc (>= 0.4 mm, fab review F2 option A, docs/reviews/fab-process-review.md). Owner decision 2026-10-07: \"Do screw holes as recommended\". Board-only (not in the schematic or BOM).")
		(tags "mountinghole M2.5")
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		(property "KiLib_Generator" "mounting_hardware/mounting_hole"
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			(uuid "cc0e4bca-cbf0-4f06-83f5-685326034d0f")
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		(attr board_only exclude_from_pos_files exclude_from_bom)
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		(fp_circle
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			(layer "Cmts.User")
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		(fp_circle
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			(fill no)
			(layer "F.CrtYd")
			(uuid "4eafc5ee-75b7-48e9-8fd8-d1bc97f4e0df")
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		(fp_text user "${REFERENCE}"
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		(pad "1" thru_hole circle
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			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(zone_connect 2)
			(uuid "f3abbcfa-aee5-4f07-84a1-95edce63db4a")
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		(descr "Capacitor SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC-7351 nominal with elongated pad for handsoldering. (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf)")
		(tags "capacitor handsolder")
		(property "Reference" "C3"
			(at 0 2.3 180)
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			(uuid "2b6ec7b2-e56d-411c-8e93-0b7d149a7291")
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		(property "Value" "22u"
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			(uuid "de648cc7-7f62-45d5-8588-6837f3394283")
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		(property "Description" "Unpolarized capacitor"
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			(layer "B.Fab")
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			(uuid "d38de9fb-4093-4bce-8e55-4d2305ccbc6c")
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		(property "KiLib_Generator" "SMD_2terminal_chip_molded"
			(at 0 0 180)
			(layer "B.SilkS")
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			(uuid "bf91578f-7276-42f6-85b9-9c65762fb18e")
			(effects
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		(property "Manufacturer" "TDK"
			(at 0 0 180)
			(layer "B.Fab")
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			(uuid "e5ca5803-72ab-44f0-8ad6-4ce6f9356776")
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		(property "MPN" "C3225X7R1E226M250AB"
			(at 0 0 180)
			(layer "B.Fab")
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			(uuid "afdc1287-64d2-41a9-8821-7a44d0b9889b")
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		(property "Distributor PN" "Digi-Key 445-C3225X7R1E226M250ABCT-ND"
			(at 0 0 180)
			(layer "B.Fab")
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		(property "Notes" "optional 22 uF 25 V X7R 1210 (+-20 %, 2.5 mm) on +5V by a fan socket; DC bias at 5 V TODO (read TDK's DC Bias Characteristic graph); Murata GRM32ER71E226KE15L when back in deep stock; see board/specs.md 5"
			(at 0 0 180)
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			(uuid "b1e14244-a074-4465-81a2-bdbd0e8f22ee")
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		(path "/b89f1ed2-be26-55bf-987e-a53143a45d60")
		(sheetname "/")
		(sheetfile "FoveaCamDuo-PCB.kicad_sch")
		(attr smd exclude_from_pos_files dnp)
		(duplicate_pad_numbers_are_jumpers no)
		(fp_line
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			(layer "B.CrtYd")
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		(fp_rect
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			(stroke
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			(fill no)
			(layer "B.Fab")
			(uuid "4ce376e9-a3ed-4d49-87a5-f0d7ffa8165c")
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		(fp_text user "${REFERENCE}"
			(at 0 0 180)
			(layer "B.Fab")
			(uuid "c79213a0-698b-46b9-8446-462d2bb6ee29")
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		(pad "1" smd roundrect
			(at -1.5625 0)
			(size 1.325 2.7)
			(layers "B.Cu" "B.Mask" "B.Paste")
			(roundrect_rratio 0.188679)
			(net "+5V")
			(pintype "passive")
			(uuid "fc90b6a0-8055-4962-862d-506ddb3c1d2c")
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		(pad "2" smd roundrect
			(at 1.5625 0)
			(size 1.325 2.7)
			(layers "B.Cu" "B.Mask" "B.Paste")
			(roundrect_rratio 0.188679)
			(net "GND")
			(pintype "passive")
			(uuid "a2985d08-7912-42c2-8f77-9ae8a6e8ca83")
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		(embedded_fonts no)
		(model "${KICAD10_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_1210_3225Metric.step"
			(offset
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			(scale
				(xyz 1 1 1)
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			(rotate
				(xyz 0 0 0)
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	)
	(footprint "FoveaCamDuo:JST_PH_S6B-PH-K_1x06_P2.00mm_Horizontal_NoSilkScreen"
		(layer "B.Cu")
		(uuid "c8753374-270b-40d2-8391-86e459bd0be8")
		(at 5 14.75 180)
		(descr "JST PH series connector, S6B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator. Extracted verbatim (pads, graphics, 3D model reference) from the footprint embedded as J_CAM0 in the original hand-drawn FoveaCamDuo-PCB.kicad_pcb (KiCad 9, git 289fb6c); not in the stock KiCad 10 library. Original library id: Connector_JST:JST_PH_S6B-PH-K_1x06_P2.00mm_Horizontal_NoSilkScreen. Drill 2026-10-07 (owner, v0.1.2): 0.80 mm finished (0.75 before): JST ePH.pdf p1 gives the PCB hole as 0.7 +0.1/0 and note 3 asks for a larger hole on glass-fibre boards; at fab tolerance a 0.75 hole can finish at 0.67 (JLCPCB -0.08) or 0.623 (Advanced PCB -0.127), below JST's 0.7. Pads stay 1.2 x 1.75 mm: plated ring 0.20 mm (>= JLCPCB 0.18, Advanced 0.178).")
		(tags "connector JST PH horizontal")
		(property "Reference" "J_CAM0"
			(at 5 2.55 0)
			(layer "B.SilkS")
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			(uuid "824b1408-447f-4325-8010-aaa736987cad")
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		(property "Value" "Conn_01x06"
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			(uuid "e1b4007e-8a5e-4128-80e9-45085ffc81e4")
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		(property "Description" "Generic connector, single row, 01x06, script generated (kicad-library-utils/schlib/autogen/connector/)"
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		(property "Manufacturer" "JST"
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			(uuid "01bc081a-bed2-4df7-845a-c4c1146ba361")
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		(property "MPN" "S6B-PH-K-S"
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			(layer "B.Fab")
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			(uuid "4b88e8bf-4f61-4f1a-8e99-2f948b7be78f")
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		(property "Distributor PN" "Digi-Key 455-1723-ND"
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		(property "Notes" "PH 2.0 mm 6-pin side entry, 4.80 mm high; mating face 6.25 mm from the pin row (JST ePH.pdf p1); plug PHR-6 + SPH-002T-P0.5S"
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		(property ki_fp_filters "Connector*:*_1x??_*")
		(path "/24ba3364-3ca8-58cf-b2fe-a5404306ba2f")
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		(sheetfile "FoveaCamDuo-PCB.kicad_sch")
		(attr through_hole)
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		(fp_line
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