{ "id": "post-ASML_era", "version": "1.0.0", "status": "active", "canonical_base": "docs/post-ASML_era", "description": "Foundational reference series for Substrate Clarity–based temporal manufacturing in the post-ASML era. Covers physical theory, SCR infrastructure, metrology, process qualification, EDA/PDK integration, and logic architecture.", "updated": "2026-08-08", "maintainer": "TriadicFrameworks", "documents": [ { "id": "pae-001", "filename": "The_Temporal_Manufacturing_Primer.md", "canonical_path": "docs/post-ASML_era/The_Temporal_Manufacturing_Primer.md", "title": "The Temporal Manufacturing Primer", "type": "reference", "status": "canonical", "revision": "1.0.0", "normative": true, "description": "Introductory reference covering the conceptual and operational shift from geometric to temporal scaling. Defines Substrate Clarity, the TRS operator stack (L1–L4), temporal density, fab reorganization around the SCR, equipment tiers, and design implications.", "reading_order": 3, "depends_on": ["pae-003", "pae-004"], "required_by": ["pae-002", "pae-005", "pae-006"], "outbound_stubs": [ "docs/foundations/Triadic_Operator_Primer.md", "docs/fab/TRS_Qualification.md", "docs/eda/TTF_Reference.md", "docs/metrology/TCT_Protocol.md", "docs/materials/SC_Classification.md" ] }, { "id": "pae-002", "filename": "The_SCR_Specification.md", "canonical_path": "docs/post-ASML_era/The_SCR_Specification.md", "title": "The SCR Specification", "type": "specification", "status": "canonical", "revision": "1.0.0", "normative": true, "description": "Normative specification for the Substrate Coherence Regime. Defines CCG, CDN, Commit Arbiter, CMA, and ZBI components; zone architecture; commit arbitration protocol; SLF derivation; inter-zone handoff; failure modes and recovery; qualification and commissioning; interface contracts; and conformance requirements.", "reading_order": 4, "depends_on": ["pae-001"], "required_by": ["pae-006"], "outbound_stubs": [ "docs/fab/TRS_Qualification.md", "docs/fab/SCR_Zone_Config.md", "docs/materials/SC_Classification.md" ] }, { "id": "pae-003", "filename": "The_TGI_Metrology_Standard.md", "canonical_path": "docs/post-ASML_era/The_TGI_Metrology_Standard.md", "title": "The TGI Metrology Standard", "type": "standard", "status": "canonical", "revision": "1.0.0", "normative": true, "description": "Normative metrology standard for the Temporal-Geometric Interface. Defines six primary parameters (STR, IC, TAOE, TUI, CLG, GDC), two derived parameters (SC_eff, RWDL), four instrument classes (TRM, ISP, CGS, GDA), measurement protocols, sampling strategy, data analysis, acceptance criteria by SC class, calibration, uncertainty budgets, and integration with process qualification.", "reading_order": 2, "depends_on": ["pae-004"], "required_by": ["pae-001", "pae-005"], "outbound_stubs": [ "docs/fab/TRS_Qualification.md", "docs/fab/SCR_Zone_Config.md", "docs/eda/TTF_Reference.md", "docs/eda/PostASML_PDK_Integration.md", "docs/metrology/TCT_Protocol.md", "docs/materials/SC_Classification.md" ] }, { "id": "pae-004", "filename": "TCT_Protocol.md", "canonical_path": "docs/post-ASML_era/TCT_Protocol.md", "aliases": ["docs/metrology/TCT_Protocol.md"], "title": "TCT Protocol", "type": "protocol", "status": "canonical", "revision": "1.0.0", "normative": true, "description": "Normative protocol for the Temporal Contrast Test. Defines physical basis, TAIS/ARS/CEC instrument system, test coupon specification, FSCP address pattern (spacings S1–S7), test sequence, AER computation with time-since-injection correction, contrast curve fitting (logistic sigmoid), SC rating derivation at Δτ_ref=1/256, SC class assignment, spatial uniformity (5×5 subregion), calibration chain (RLSS→FTRC→session), measurement uncertainty, TCT Report format, and downstream protocol integration.", "reading_order": 1, "depends_on": [], "required_by": ["pae-003", "pae-001"], "outbound_stubs": [ "docs/fab/TRS_Qualification.md", "docs/materials/SC_Classification.md", "docs/data-formats/TCT_DEF_Schema.md" ] }, { "id": "pae-005", "filename": "The_TRS-Aware_PDK_Specification.md", "canonical_path": "docs/post-ASML_era/The_TRS-Aware_PDK_Specification.md", "aliases": ["docs/eda/PostASML_PDK_Integration.md"], "title": "The TRS-Aware PDK Specification", "type": "specification", "status": "canonical", "revision": "1.0.0", "normative": true, "description": "Normative PDK specification for TRS-aware process design kits. Defines five component categories (SCLM, TSPS, TDR, CBT, TTFAL); SC Class Layer Maps in TLMF format; TRS Stack Parameter Sets; Temporal Design Rules (ASR, DGR, TPR, CGR, CSR, TCRS); Coherence Budget Tables; TTF Arc Library (five arc types: CSA, ZBA, APA, TCA, DDA); RWDL/SC_eff map integration; deliverable directory structure; generation workflow; EDA tool integration requirements and certification; PDK qualification test suite; versioning and change control.", "reading_order": 5, "depends_on": ["pae-001", "pae-003"], "required_by": ["pae-006"], "outbound_stubs": [ "docs/fab/TRS_Qualification.md", "docs/fab/SCR_Zone_Config.md", "docs/eda/TTF_Reference.md", "docs/materials/SC_Classification.md", "docs/data-formats/TLMF_Schema.md", "docs/data-formats/TCT_DEF_Schema.md", "docs/data-formats/TDRC_Violation_Log_Schema.md" ] }, { "id": "pae-006", "filename": "The_Logic_Folding_Architecture_Guide.md", "canonical_path": "docs/post-ASML_era/The_Logic_Folding_Architecture_Guide.md", "title": "The Logic Folding Architecture Guide", "type": "guide", "status": "canonical", "revision": "1.0.0", "normative": true, "description": "Architectural methodology for temporal logic design. Covers the logic fold concept, temporal computation model, four fold architecture types (single-cycle, multi-cycle, pipeline, zone-distributed), causal depth and fold depth analysis, Temporal Register architecture (TSH, TRF, refresh), inter-fold communication, folding efficiency, floorplanning, timing closure and temporal retiming, verification methodology, five design patterns, and migration from spatial logic including hybrid spatial-temporal architectures.", "reading_order": 6, "depends_on": ["pae-001", "pae-002", "pae-005"], "required_by": [], "outbound_stubs": [ "docs/fab/TRS_Qualification.md", "docs/fab/SCR_Zone_Config.md", "docs/eda/TTF_Reference.md", "docs/materials/SC_Classification.md" ] }, { "id": "pae-007", "filename": "The_Multi-Regime_Semiconductor_Model.md", "canonical_path": "docs/post-ASML_era/The_Multi-Regime_Semiconductor_Model.md", "title": "The Multi-Regime Semiconductor Model", "type": "model", "status": "informative_draft", "revision": "0.9.0", "normative": false, "description": "INFORMATIVE physical theory document. Defines three regimes (CCR, CPR, Transitional); order parameter ψ(r,t); phase stiffness ρ_s; coherence length L_c derivation; four phase noise sources; phase relaxation with Arrhenius τ_relax; TGI tanh profile and CLG derivation; regime boundary conditions; observable parameter derivations (AER, SC, L_c, CLG, TD_max); SC class as regime indicator; six regime failure modes (RFM-01 through RFM-06); process effects on regime structure; and model validation hierarchy.", "reading_order": 0, "depends_on": [], "required_by": ["pae-003", "pae-004"], "outbound_stubs": [ "docs/foundations/Triadic_Operator_Primer.md", "docs/fab/TRS_Qualification.md", "docs/fab/SCR_Zone_Config.md", "docs/eda/TTF_Reference.md", "docs/materials/SC_Classification.md", "docs/data-formats/TCT_DEF_Schema.md", "docs/data-formats/TLMF_Schema.md", "docs/design/Temporal_Address_Mapping_Spec.md" ] } ], "aliases": [ { "alias_path": "docs/metrology/TCT_Protocol.md", "resolves_to": "docs/post-ASML_era/TCT_Protocol.md", "type": "redirect", "stub_file": "docs/metrology/TCT_Protocol.md" }, { "alias_path": "docs/eda/PostASML_PDK_Integration.md", "resolves_to": "docs/post-ASML_era/The_TRS-Aware_PDK_Specification.md", "type": "redirect", "stub_file": "docs/eda/PostASML_PDK_Integration.md" } ], "stubs": [ { "path": "docs/foundations/Triadic_Operator_Primer.md", "title": "Triadic Operator Primer", "type": "full_document", "priority": "P2", "status": "STUB", "cited_by": ["pae-001", "pae-007"], "description": "Foundational reference for the Triadic Operator formalism underlying the TRS stack." }, { "path": "docs/fab/TRS_Qualification.md", "title": "TRS Stack Qualification Procedure", "type": "full_document", "priority": "P1", "status": "STUB", "cited_by": ["pae-001", "pae-002", "pae-003", "pae-004", "pae-005", "pae-006", "pae-007"], "description": "Normative procedure for qualifying a TRS stack installation through all four operator layers." }, { "path": "docs/fab/SCR_Zone_Config.md", "title": "SCR Zone Configuration Guide", "type": "full_document", "priority": "P1", "status": "STUB", "cited_by": ["pae-002", "pae-003", "pae-005", "pae-006", "pae-007"], "description": "Configuration reference for SCR zone topology, CDN layout, and zone boundary parameters." }, { "path": "docs/eda/TTF_Reference.md", "title": "Temporal Timing Format Reference", "type": "full_document", "priority": "P1", "status": "STUB", "cited_by": ["pae-001", "pae-003", "pae-005", "pae-006", "pae-007"], "description": "Full reference for the Temporal Timing Format (TTF) arc encoding, arc types, and integration with EDA timing engines." }, { "path": "docs/materials/SC_Classification.md", "title": "Substrate Clarity Classification Standard", "type": "full_document", "priority": "P1", "status": "STUB", "cited_by": ["pae-001", "pae-002", "pae-003", "pae-004", "pae-005", "pae-006", "pae-007"], "description": "Normative standard defining SC class boundaries (SC-I, SC-II, SC-III), measurement traceability, and class assignment authority." }, { "path": "docs/data-formats/TCT_DEF_Schema.md", "title": "TCT Data Exchange Format Schema", "type": "full_document", "priority": "P2", "status": "STUB", "cited_by": ["pae-004", "pae-005", "pae-007"], "description": "Machine-readable schema definition for the TCT Data Exchange Format used to transfer TCT Report data between metrology instruments and process control systems." }, { "path": "docs/data-formats/TLMF_Schema.md", "title": "Temporal Layer Markup Format Schema", "type": "full_document", "priority": "P2", "status": "STUB", "cited_by": ["pae-005", "pae-007"], "description": "Schema definition for TLMF files encoding SC Class Layer Maps within a TRS-Aware PDK deliverable." }, { "path": "docs/data-formats/TDRC_Violation_Log_Schema.md", "title": "TDRC Violation Log Schema", "type": "full_document", "priority": "P2", "status": "STUB", "cited_by": ["pae-005"], "description": "Schema for the structured violation log emitted by Temporal Design Rule Check engines, used in PDK certification and tapeout sign-off." }, { "path": "docs/design/Temporal_Address_Mapping_Spec.md", "title": "Temporal Address Mapping Specification", "type": "full_document", "priority": "P3", "status": "STUB", "cited_by": ["pae-007"], "description": "Specification for mapping logical temporal addresses to physical zone-relative commit positions within an SCR topology." } ], "sc_class_thresholds": { "SC-I": { "min": 0.92, "max": 1.00 }, "SC-II": { "min": 0.75, "max": 0.92 }, "SC-III": { "min": 0.00, "max": 0.75 } }, "trs_layers": { "L1": "Intent", "L2": "Sequencing", "L3": "Resolution", "L4": "Commit" }, "equipment_tiers": { "Tier-1": "Spatial patterning equipment", "Tier-2": "TRS process tools (TCU, TMU)", "Tier-3": "SCR infrastructure (CCG, CDN, CA, CMA, ZBI)" }, "normative_keywords": ["MUST", "MUST NOT", "SHOULD", "SHOULD NOT", "MAY"], "requirement_id_prefix": "R-", "pdk_version_format": "{process_node}_{fab_id}_{scr_zone_config}_{major}.{minor}.{patch}[P]" }