48 #ifndef __DRV_BH1745_H__
49 #define __DRV_BH1745_H__
51 #include "nrf_drv_twi.h"
54 #define REG_SYSTEM_CONTROL 0x40
55 #define REG_MODE_CONTROL1 0x41
56 #define REG_MODE_CONTROL2 0x42
57 #define REG_MODE_CONTROL3 0x44
58 #define REG_RED_DATA_LSBs 0x50
59 #define REG_RED_DATA_MSBs 0x51
60 #define REG_GREEN_DATA_LSB 0x52
61 #define REG_GREEN_DATA_MSB 0x53
62 #define REG_BLUE_DATA_LSB 0x54
63 #define REG_BLUE_DATA_MSB 0x55
64 #define REG_CLEAR_DATA_LSB 0x56
65 #define REG_CLEAR_DATA_MSB 0x57
66 #define REG_DINT_DATA_LSB 0x58
67 #define REG_DINT_DATA_MSB 0x59
68 #define REG_INTERRUPT 0x60
69 #define REG_PERSISTENCE 0x61
70 #define REG_TH_LSB 0x62
71 #define REG_TH_MSB 0x63
72 #define REG_TL_LSB 0x64
73 #define REG_TL_MSB 0x65
74 #define REG_MANUFACTURER_ID 0x92
76 #define REG_SYSTEM_CONTROL_PART_ID_Msk 0x3F
77 #define REG_SYSTEM_CONTROL_SW_RESET_Msk 0x80
78 #define REG_SYSTEM_CONTROL_INT_RESET_Msk 0x40
80 #define REG_MODE_CONTROL1_MEAS_TIME_Msk 0x07
82 #define REG_MODE_CONTROL2_VALID_Msk 0x80
83 #define REG_MODE_CONTROL2_RGBC_EN_Msk 0x10
84 #define REG_MODE_CONTROL2_GAIN_Msk 0x03
86 #define REG_INTERRUPT_STATUS_Msk 0x80
87 #define REG_INTERRUPT_LATCH_Msk 0x10
88 #define REG_INTERRUPT_SOURCE_Msk 0x0C
89 #define REG_INTERRUPT_ENABLE_Msk 0x01
91 #define REG_PERSISTENCE_PERSISTENCE_Msk 0x03
107 DRV_BH1745_MEAS_TIME_160MS,
108 DRV_BH1745_MEAS_TIME_320MS,
109 DRV_BH1745_MEAS_TIME_640MS,
110 DRV_BH1745_MEAS_TIME_1280MS,
111 DRV_BH1745_MEAS_TIME_2560MS,
112 DRV_BH1745_MEAS_TIME_5120MS