# Overview

Use `fxrstor64` to load the FPU, MMX, XMM, and MXCSR state (512 bytes) from a
wildly slow MMIO region (generally a mailbox register in the VGA space).  The
source address is offset so that the MXCSR dword (offset 24 in the image) reads
back with its reserved bits clear, avoiding a #GP fault.  Every one of the 512
bytes must be pulled across the PCIe fabric before this single, uninterruptible
instruction can retire.

```asm
movl $0xfcc68830, %rsi
fxrstor64 %rsi
```

This is a standalone tool — build it from the repo root with `make fxrstor64`
(or `make` to build everything), then run the binary directly:

```sh
sudo ./bin/fxrstor64/fxrstor64      # prints min cycles
sudo ./bin/fxrstor64/fxrstor64 -v   # verbose: address, baseline, min/avg
```

# Score

**Score**: 74,584,168,512 cycles

**Time**: 23.354502677 seconds

# Contender

CPU: `AMD Ryzen 7 5800H with Radeon Graphics`
Manufacturer: `Trigkey`
Product Name: `S5`

# Credits

Identified with [mmiotic](github.com/xoreaxeaxeax/mmiotic)