diff -Naur u-boot-2017.11/arch/arm/cpu/arm926ejs/mxs/mxs.c u-boot-2017.11-lcy/arch/arm/cpu/arm926ejs/mxs/mxs.c --- u-boot-2017.11/arch/arm/cpu/arm926ejs/mxs/mxs.c 2017-11-14 09:08:06.000000000 +0800 +++ u-boot-2017.11-lcy/arch/arm/cpu/arm926ejs/mxs/mxs.c 2018-06-27 12:53:52.483099685 +0800 @@ -175,6 +175,46 @@ } } +static uint8_t mxs_get_bootmode_index(void) +{ + uint8_t bootmode = 0; + int i; + uint8_t masked; + +#if defined(CONFIG_MX23) + /* Setup IOMUX of bootmode pads to GPIO */ + mxs_iomux_setup_multiple_pads(iomux_boot, ARRAY_SIZE(iomux_boot)); + + /* Setup bootmode pins as GPIO input */ + gpio_direction_input(MX23_PAD_LCD_D00__GPIO_1_0); + gpio_direction_input(MX23_PAD_LCD_D01__GPIO_1_1); + gpio_direction_input(MX23_PAD_LCD_D02__GPIO_1_2); + gpio_direction_input(MX23_PAD_LCD_D03__GPIO_1_3); + gpio_direction_input(MX23_PAD_LCD_D05__GPIO_1_5); + + /* Read bootmode pads */ + bootmode |= (gpio_get_value(MX23_PAD_LCD_D00__GPIO_1_0) ? 1 : 0) << 0; + bootmode |= (gpio_get_value(MX23_PAD_LCD_D01__GPIO_1_1) ? 1 : 0) << 1; + bootmode |= (gpio_get_value(MX23_PAD_LCD_D02__GPIO_1_2) ? 1 : 0) << 2; + bootmode |= (gpio_get_value(MX23_PAD_LCD_D03__GPIO_1_3) ? 1 : 0) << 3; + bootmode |= (gpio_get_value(MX23_PAD_LCD_D05__GPIO_1_5) ? 1 : 0) << 5; +#elif defined(CONFIG_MX28) + /* The global boot mode will be detected by ROM code and its value + * is stored at the fixed address 0x00019BF0 in OCRAM. + */ +#define GLOBAL_BOOT_MODE_ADDR 0x00019BF0 + bootmode = __raw_readl(GLOBAL_BOOT_MODE_ADDR); +#endif + + for (i = 0; i < ARRAY_SIZE(mxs_boot_modes); i++) { + masked = bootmode & mxs_boot_modes[i].boot_mask; + if (masked == mxs_boot_modes[i].boot_pads) + break; + } + + return i; +} + int print_cpuinfo(void) { u32 cpurev; @@ -182,12 +222,14 @@ ((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf); cpurev = get_cpu_rev(); + data->boot_mode_idx = mxs_get_bootmode_index(); printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n", get_imx_type((cpurev & 0xFF000) >> 12), (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0, mxc_get_clock(MXC_ARM_CLK) / 1000000); printf("BOOT: %s\n", mxs_boot_modes[data->boot_mode_idx].mode); + do_mx28_showclocks(0,0,0,0); return 0; } #endif @@ -286,6 +328,7 @@ hang(); } + data->mem_dram_size = 64 * 1024 * 1024; gd->ram_size = data->mem_dram_size; return 0; } diff -Naur u-boot-2017.11/board/freescale/mx28evk/mx28evk.c u-boot-2017.11-lcy/board/freescale/mx28evk/mx28evk.c --- u-boot-2017.11/board/freescale/mx28evk/mx28evk.c 2017-11-14 09:08:06.000000000 +0800 +++ u-boot-2017.11-lcy/board/freescale/mx28evk/mx28evk.c 2018-06-27 19:32:07.435529895 +0800 @@ -26,6 +26,14 @@ DECLARE_GLOBAL_DATA_PTR; +#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) +#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL) +#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) + + /* * Functions */ @@ -41,18 +49,164 @@ /* SSP2 clock at 160MHz */ mxs_set_sspclk(MXC_SSPCLK2, 160000, 0); + + + /* DUART */ + mxs_iomux_setup_pad(MX28_PAD_PWM0__DUART_RX); + mxs_iomux_setup_pad(MX28_PAD_PWM1__DUART_TX); + + udelay(100); + /* MMC0 */ + mxs_iomux_setup_pad(MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0); + mxs_iomux_setup_pad(MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0); + mxs_iomux_setup_pad(MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0); + mxs_iomux_setup_pad(MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0); + mxs_iomux_setup_pad(MX28_PAD_SSP0_DATA4__SSP0_D4 | MUX_CONFIG_SSP0); + mxs_iomux_setup_pad(MX28_PAD_SSP0_DATA5__SSP0_D5 | MUX_CONFIG_SSP0); + mxs_iomux_setup_pad(MX28_PAD_SSP0_DATA6__SSP0_D6 | MUX_CONFIG_SSP0); + mxs_iomux_setup_pad(MX28_PAD_SSP0_DATA7__SSP0_D7 | MUX_CONFIG_SSP0); + mxs_iomux_setup_pad(MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0); + mxs_iomux_setup_pad(MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL)); + mxs_iomux_setup_pad(MX28_PAD_SSP0_SCK__SSP0_SCK | + (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL)); + mxs_iomux_setup_pad(MX28_PAD_GPMI_CE1N__GPIO_0_17 | MUX_CONFIG_SSP0); + + +#ifdef CONFIG_NAND_MXS + /* GPMI NAND */ + mxs_iomux_setup_pad(MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI); + mxs_iomux_setup_pad(MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI); + mxs_iomux_setup_pad(MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI); + mxs_iomux_setup_pad(MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI); + mxs_iomux_setup_pad(MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI); + mxs_iomux_setup_pad(MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI); + mxs_iomux_setup_pad(MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI); + mxs_iomux_setup_pad(MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI); + mxs_iomux_setup_pad(MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI); + mxs_iomux_setup_pad(MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI); + mxs_iomux_setup_pad(MX28_PAD_GPMI_RDN__GPMI_RDN | + (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)); + mxs_iomux_setup_pad(MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI); + mxs_iomux_setup_pad(MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI); + mxs_iomux_setup_pad(MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI); + mxs_iomux_setup_pad(MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI); +#endif + + /* FEC0 */ + mxs_iomux_setup_pad(MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET); + mxs_iomux_setup_pad(MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET); + mxs_iomux_setup_pad(MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET); + mxs_iomux_setup_pad(MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET); + mxs_iomux_setup_pad(MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET); + mxs_iomux_setup_pad(MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET); + mxs_iomux_setup_pad(MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET); + mxs_iomux_setup_pad(MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET); + mxs_iomux_setup_pad(MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET); + /* FEC0 Reset */ + mxs_iomux_setup_pad(MX28_PAD_LCD_D16__GPIO_1_16 | + (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP)); + + /* EMI */ + mxs_iomux_setup_pad(MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI); + mxs_iomux_setup_pad(MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI); + mxs_iomux_setup_pad(MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI); + mxs_iomux_setup_pad(MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI); + mxs_iomux_setup_pad(MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI); + mxs_iomux_setup_pad(MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI); + mxs_iomux_setup_pad(MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI); + mxs_iomux_setup_pad(MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI); + mxs_iomux_setup_pad(MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI); + mxs_iomux_setup_pad(MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI); + mxs_iomux_setup_pad(MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI); + mxs_iomux_setup_pad(MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI); + mxs_iomux_setup_pad(MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI); + mxs_iomux_setup_pad(MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI); + mxs_iomux_setup_pad(MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI); + mxs_iomux_setup_pad(MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI); + mxs_iomux_setup_pad(MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI); + mxs_iomux_setup_pad(MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI); + mxs_iomux_setup_pad(MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI); + mxs_iomux_setup_pad(MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI); + mxs_iomux_setup_pad(MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI); + mxs_iomux_setup_pad(MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI); + mxs_iomux_setup_pad(MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI); + mxs_iomux_setup_pad(MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI); + + mxs_iomux_setup_pad(MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI); + mxs_iomux_setup_pad(MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI); + mxs_iomux_setup_pad(MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI); + mxs_iomux_setup_pad(MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI); + mxs_iomux_setup_pad(MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI); + mxs_iomux_setup_pad(MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI); + mxs_iomux_setup_pad(MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI); + mxs_iomux_setup_pad(MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI); + mxs_iomux_setup_pad(MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI); + mxs_iomux_setup_pad(MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI); + mxs_iomux_setup_pad(MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI); + mxs_iomux_setup_pad(MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI); + mxs_iomux_setup_pad(MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI); + mxs_iomux_setup_pad(MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI); + mxs_iomux_setup_pad(MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI); + mxs_iomux_setup_pad(MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI); + mxs_iomux_setup_pad(MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI); + mxs_iomux_setup_pad(MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI); + mxs_iomux_setup_pad(MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI); + mxs_iomux_setup_pad(MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI); + mxs_iomux_setup_pad(MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI); + mxs_iomux_setup_pad(MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI); + mxs_iomux_setup_pad(MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI); + + /* I2C */ + mxs_iomux_setup_pad(MX28_PAD_I2C0_SCL__I2C0_SCL); + mxs_iomux_setup_pad(MX28_PAD_I2C0_SDA__I2C0_SDA); + mxs_iomux_setup_pad(MX28_PAD_PWM0__I2C1_SCL); + mxs_iomux_setup_pad(MX28_PAD_PWM1__I2C1_SDA); + + /* LCD */ + mxs_iomux_setup_pad(MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD); + mxs_iomux_setup_pad(MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD); + mxs_iomux_setup_pad(MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD); + mxs_iomux_setup_pad(MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD); + mxs_iomux_setup_pad(MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD); + mxs_iomux_setup_pad(MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD); + mxs_iomux_setup_pad(MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD); + mxs_iomux_setup_pad(MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD); + mxs_iomux_setup_pad(MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD); + mxs_iomux_setup_pad(MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD); + mxs_iomux_setup_pad(MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD); + mxs_iomux_setup_pad(MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD); + mxs_iomux_setup_pad(MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD); + mxs_iomux_setup_pad(MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD); + mxs_iomux_setup_pad(MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD); + mxs_iomux_setup_pad(MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD); + mxs_iomux_setup_pad(MX28_PAD_LCD_RD_E__LCD_VSYNC | MUX_CONFIG_LCD); + mxs_iomux_setup_pad(MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MUX_CONFIG_LCD); + mxs_iomux_setup_pad(MX28_PAD_LCD_RS__LCD_DOTCLK | MUX_CONFIG_LCD); + mxs_iomux_setup_pad(MX28_PAD_LCD_CS__LCD_ENABLE | MUX_CONFIG_LCD); + mxs_iomux_setup_pad(MX28_PAD_LCD_RESET__GPIO_3_30 | MUX_CONFIG_LCD); + mxs_iomux_setup_pad(MX28_PAD_PWM3__GPIO_3_28 | MUX_CONFIG_LCD); /* LCD contrast */ + + +#ifdef CONFIG_CMD_USB + mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT); + mxs_iomux_setup_pad(MX28_PAD_SSP2_SS2__USB0_OVERCURRENT); +#endif +/* #ifdef CONFIG_CMD_USB mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT); mxs_iomux_setup_pad(MX28_PAD_AUART2_RX__GPIO_3_8 | MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL); gpio_direction_output(MX28_PAD_AUART2_RX__GPIO_3_8, 1); #endif +*/ /* Power on LCD */ gpio_direction_output(MX28_PAD_LCD_RESET__GPIO_3_30, 1); /* Set contrast to maximum */ - gpio_direction_output(MX28_PAD_PWM2__GPIO_3_18, 1); + //gpio_direction_output(MX28_PAD_PWM2__GPIO_3_18, 1); + gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 1); return 0; } @@ -77,14 +231,20 @@ printf("MXS MMC: Invalid card selected (card id = %d)\n", id); return 1; } - +/* return gpio_get_value(MX28_PAD_SSP1_SCK__GPIO_2_12); +*/ + return gpio_get_value(MX28_PAD_GPMI_CE1N__GPIO_0_17); } int board_mmc_init(bd_t *bis) { /* Configure WP as input */ +/* gpio_direction_input(MX28_PAD_SSP1_SCK__GPIO_2_12); +*/ + gpio_direction_input(MX28_PAD_GPMI_CE1N__GPIO_0_17); + /* Configure MMC0 Power Enable */ gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0); diff -Naur u-boot-2017.11/include/configs/mx28evk.h u-boot-2017.11-lcy/include/configs/mx28evk.h --- u-boot-2017.11/include/configs/mx28evk.h 2017-11-14 09:08:06.000000000 +0800 +++ u-boot-2017.11-lcy/include/configs/mx28evk.h 2018-06-29 12:06:21.050817688 +0800 @@ -21,6 +21,10 @@ #define PHYS_SDRAM_1_SIZE 0x40000000 /* Max 1 GB RAM */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_DCACHE_OFF + /* Environment */ #ifndef CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_SIZE (16 * 1024) @@ -40,7 +44,7 @@ #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE #define CONFIG_ENV_SECT_SIZE (128 * 1024) #define CONFIG_ENV_RANGE (512 * 1024) -#define CONFIG_ENV_OFFSET 0x300000 +#define CONFIG_ENV_OFFSET 0xc00000 #define CONFIG_ENV_OFFSET_REDUND \ (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) #endif @@ -97,6 +101,7 @@ #endif /* Framebuffer support */ +/* #ifdef CONFIG_VIDEO #define CONFIG_VIDEO_LOGO #define CONFIG_SPLASH_SCREEN @@ -105,14 +110,32 @@ #define CONFIG_VIDEO_BMP_GZIP #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (512 << 10) #endif +*/ + /* Boot Linux */ #define CONFIG_BOOTFILE "uImage" #define CONFIG_LOADADDR 0x42000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define MTDIDS_DEFAULT "nand0=gpmi-nand" + +#define MTDPARTS_DEFAULT "mtdparts=gpmi-nand:12m(boot),"\ + "512k(env),"\ + "512k(reserve),"\ + "2m(bmp),"\ + "512k(reserve),"\ + "64m(rootfs),"\ + "-(opt)" + + /* Extra Environment */ #define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel=uImage\0" \ + "kernelsize=0x300000\0" \ + "showbitmap=0\0" \ + "kerneladdr=0x00200000\0" \ + "kerneladdr2=0x0078000\0" \ "ubifs_file=filesystem.ubifs\0" \ "update_nand_full_filename=u-boot.nand\0" \ "update_nand_firmware_filename=u-boot.sb\0" \ @@ -176,13 +199,26 @@ "ubi create filesystem; " \ "ubi write ${loadaddr} filesystem ${filesize}\0" \ "nandargs=setenv bootargs console=${console_mainline},${baudrate} " \ - "rootfstype=ubifs ubi.mtd=6 root=ubi0_0 ${mtdparts}\0" \ + "rootfstype=ubifs ubi.mtd=5 root=ubi0_0 ${mtdparts}\0" \ + "default_args="\ + "setenv bootargs console=${console_mainline},${baudrate}n8 rootfstype=ubifs ubi.mtd=5 root=ubi0:rootfs rw mem=64M\0" \ + "nand_boot="\ + "mtdparts default;" \ + "run default_args;" \ + "nand read.jffs2 ${loadaddr} ${kerneladdr} ${kernelsize};" \ + "bootz;" \ + "nand read.jffs2 ${loadaddr} ${kerneladdr2} ${kernelsize};" \ + "bootz;\0" \ + "sd_boot="\ + "mtdparts default;"\ + "run default_args;"\ + "fatload mmc 0:1 ${loadaddr} zImage_dtb;bootz;\0"\ "nandboot=" /* Boot from NAND */ \ "mtdparts default; " \ "run nandargs; " \ - "nand read ${loadaddr} kernel 0x00400000; " \ + "nand read.jffs2 ${loadaddr} kernel 0x00400000; " \ "if test ${boot_fdt} = yes; then " \ - "nand read ${fdt_addr} fdt 0x00080000; " \ + "nand read.jffs2 ${fdt_addr} fdt 0x00080000; " \ "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = no; then " \ @@ -259,6 +295,9 @@ "bootz; " \ "fi;\0" +#define CONFIG_BOOTCOMMAND "run nand_boot" + +/* #define CONFIG_BOOTCOMMAND \ "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ @@ -270,6 +309,7 @@ "fi; " \ "fi; " \ "else run netboot; fi" + */ /* The rest of the configuration is shared */ #include diff -Naur u-boot-2017.11/include/configs/mxs.h u-boot-2017.11-lcy/include/configs/mxs.h --- u-boot-2017.11/include/configs/mxs.h 2017-11-14 09:08:06.000000000 +0800 +++ u-boot-2017.11-lcy/include/configs/mxs.h 2018-06-29 10:04:02.005610188 +0800 @@ -78,7 +78,7 @@ * As for the SPL, we must avoid the first 4 KiB as well, but we load the * IVT and CST to 0x8000, so we don't need to waste the subsequent 4 KiB. */ -#define CONFIG_SYS_TEXT_BASE 0x40002000 +#define CONFIG_SYS_TEXT_BASE 0x40000000 #define CONFIG_SPL_TEXT_BASE 0x00001000 /* U-Boot general configuration */ @@ -138,9 +138,11 @@ /* NAND */ #ifdef CONFIG_CMD_NAND #define CONFIG_NAND_MXS +#define NAND_MAX_CHIPS 8 #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x60000000 +#define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_MTD_PARTITIONS #endif /* OCOTP */