vendor_name = ModelSim
source_file = 1, E:/altera/15.0/Project/2020/UART/uart_top/uart_top.v
source_file = 1, E:/altera/15.0/Project/2020/UART/uart_top/uarttx.v
source_file = 1, E:/altera/15.0/Project/2020/UART/uart_top/uartrx.v
source_file = 1, E:/altera/15.0/Project/2020/UART/uart_top/clkdiv.v
source_file = 1, E:/altera/15.0/Project/2020/UART/uart_top/db/uart_top.cbx.xml
design_name = uart_top
instance = comp, \clkout~output , clkout~output, uart_top, 1
instance = comp, \en~output , en~output, uart_top, 1
instance = comp, \dataerror~output , dataerror~output, uart_top, 1
instance = comp, \framerror~output , framerror~output, uart_top, 1
instance = comp, \idle~output , idle~output, uart_top, 1
instance = comp, \txd~output , txd~output, uart_top, 1
instance = comp, \data[0]~output , data[0]~output, uart_top, 1
instance = comp, \data[1]~output , data[1]~output, uart_top, 1
instance = comp, \data[2]~output , data[2]~output, uart_top, 1
instance = comp, \data[3]~output , data[3]~output, uart_top, 1
instance = comp, \data[4]~output , data[4]~output, uart_top, 1
instance = comp, \data[5]~output , data[5]~output, uart_top, 1
instance = comp, \data[6]~output , data[6]~output, uart_top, 1
instance = comp, \data[7]~output , data[7]~output, uart_top, 1
instance = comp, \clk~input , clk~input, uart_top, 1
instance = comp, \clk~inputclkctrl , clk~inputclkctrl, uart_top, 1
instance = comp, \b2v_inst|cnt[0]~16 , b2v_inst|cnt[0]~16, uart_top, 1
instance = comp, \b2v_inst|LessThan0~2 , b2v_inst|LessThan0~2, uart_top, 1
instance = comp, \rst~input , rst~input, uart_top, 1
instance = comp, \b2v_inst|LessThan0~0 , b2v_inst|LessThan0~0, uart_top, 1
instance = comp, \b2v_inst|LessThan0~1 , b2v_inst|LessThan0~1, uart_top, 1
instance = comp, \b2v_inst|cnt[15]~20 , b2v_inst|cnt[15]~20, uart_top, 1
instance = comp, \b2v_inst|cnt[0] , b2v_inst|cnt[0], uart_top, 1
instance = comp, \b2v_inst|cnt[1]~18 , b2v_inst|cnt[1]~18, uart_top, 1
instance = comp, \b2v_inst|cnt[1] , b2v_inst|cnt[1], uart_top, 1
instance = comp, \b2v_inst|cnt[2]~21 , b2v_inst|cnt[2]~21, uart_top, 1
instance = comp, \b2v_inst|cnt[2] , b2v_inst|cnt[2], uart_top, 1
instance = comp, \b2v_inst|cnt[3]~23 , b2v_inst|cnt[3]~23, uart_top, 1
instance = comp, \b2v_inst|cnt[3] , b2v_inst|cnt[3], uart_top, 1
instance = comp, \b2v_inst|cnt[4]~25 , b2v_inst|cnt[4]~25, uart_top, 1
instance = comp, \b2v_inst|cnt[4] , b2v_inst|cnt[4], uart_top, 1
instance = comp, \b2v_inst|cnt[5]~27 , b2v_inst|cnt[5]~27, uart_top, 1
instance = comp, \b2v_inst|cnt[5] , b2v_inst|cnt[5], uart_top, 1
instance = comp, \b2v_inst|cnt[6]~29 , b2v_inst|cnt[6]~29, uart_top, 1
instance = comp, \b2v_inst|cnt[6] , b2v_inst|cnt[6], uart_top, 1
instance = comp, \b2v_inst|cnt[7]~31 , b2v_inst|cnt[7]~31, uart_top, 1
instance = comp, \b2v_inst|cnt[7] , b2v_inst|cnt[7], uart_top, 1
instance = comp, \b2v_inst|cnt[8]~33 , b2v_inst|cnt[8]~33, uart_top, 1
instance = comp, \b2v_inst|cnt[8] , b2v_inst|cnt[8], uart_top, 1
instance = comp, \b2v_inst|cnt[9]~35 , b2v_inst|cnt[9]~35, uart_top, 1
instance = comp, \b2v_inst|cnt[9] , b2v_inst|cnt[9], uart_top, 1
instance = comp, \b2v_inst|cnt[10]~37 , b2v_inst|cnt[10]~37, uart_top, 1
instance = comp, \b2v_inst|cnt[10] , b2v_inst|cnt[10], uart_top, 1
instance = comp, \b2v_inst|cnt[11]~39 , b2v_inst|cnt[11]~39, uart_top, 1
instance = comp, \b2v_inst|cnt[11] , b2v_inst|cnt[11], uart_top, 1
instance = comp, \b2v_inst|cnt[12]~41 , b2v_inst|cnt[12]~41, uart_top, 1
instance = comp, \b2v_inst|cnt[12] , b2v_inst|cnt[12], uart_top, 1
instance = comp, \b2v_inst|cnt[13]~43 , b2v_inst|cnt[13]~43, uart_top, 1
instance = comp, \b2v_inst|cnt[13] , b2v_inst|cnt[13], uart_top, 1
instance = comp, \b2v_inst|cnt[14]~45 , b2v_inst|cnt[14]~45, uart_top, 1
instance = comp, \b2v_inst|cnt[14] , b2v_inst|cnt[14], uart_top, 1
instance = comp, \b2v_inst|cnt[15]~47 , b2v_inst|cnt[15]~47, uart_top, 1
instance = comp, \b2v_inst|cnt[15] , b2v_inst|cnt[15], uart_top, 1
instance = comp, \b2v_inst|LessThan0~3 , b2v_inst|LessThan0~3, uart_top, 1
instance = comp, \b2v_inst|clkout~0 , b2v_inst|clkout~0, uart_top, 1
instance = comp, \b2v_inst|clkout , b2v_inst|clkout, uart_top, 1
instance = comp, \b2v_inst|clkout~clkctrl , b2v_inst|clkout~clkctrl, uart_top, 1
instance = comp, \b2v_inst1|Add0~0 , b2v_inst1|Add0~0, uart_top, 1
instance = comp, \b2v_inst1|cnt~10 , b2v_inst1|cnt~10, uart_top, 1
instance = comp, \rst~inputclkctrl , rst~inputclkctrl, uart_top, 1
instance = comp, \b2v_inst1|cnt[0] , b2v_inst1|cnt[0], uart_top, 1
instance = comp, \b2v_inst1|Add0~2 , b2v_inst1|Add0~2, uart_top, 1
instance = comp, \b2v_inst1|Add0~4 , b2v_inst1|Add0~4, uart_top, 1
instance = comp, \b2v_inst1|cnt~8 , b2v_inst1|cnt~8, uart_top, 1
instance = comp, \b2v_inst1|cnt[2] , b2v_inst1|cnt[2], uart_top, 1
instance = comp, \b2v_inst1|Add0~6 , b2v_inst1|Add0~6, uart_top, 1
instance = comp, \b2v_inst1|Add0~8 , b2v_inst1|Add0~8, uart_top, 1
instance = comp, \b2v_inst1|Add0~10 , b2v_inst1|Add0~10, uart_top, 1
instance = comp, \b2v_inst1|cnt~13 , b2v_inst1|cnt~13, uart_top, 1
instance = comp, \b2v_inst1|cnt~4 , b2v_inst1|cnt~4, uart_top, 1
instance = comp, \b2v_inst1|cnt[5] , b2v_inst1|cnt[5], uart_top, 1
instance = comp, \b2v_inst1|Add0~12 , b2v_inst1|Add0~12, uart_top, 1
instance = comp, \b2v_inst1|Add0~14 , b2v_inst1|Add0~14, uart_top, 1
instance = comp, \b2v_inst1|cnt~3 , b2v_inst1|cnt~3, uart_top, 1
instance = comp, \b2v_inst1|cnt[7] , b2v_inst1|cnt[7], uart_top, 1
instance = comp, \b2v_inst1|cnt~14 , b2v_inst1|cnt~14, uart_top, 1
instance = comp, \b2v_inst1|cnt~15 , b2v_inst1|cnt~15, uart_top, 1
instance = comp, \b2v_inst1|cnt[4] , b2v_inst1|cnt[4], uart_top, 1
instance = comp, \b2v_inst1|cnt~1 , b2v_inst1|cnt~1, uart_top, 1
instance = comp, \b2v_inst1|cnt~2 , b2v_inst1|cnt~2, uart_top, 1
instance = comp, \b2v_inst1|cnt[3]~5 , b2v_inst1|cnt[3]~5, uart_top, 1
instance = comp, \b2v_inst1|cnt~11 , b2v_inst1|cnt~11, uart_top, 1
instance = comp, \b2v_inst1|cnt~12 , b2v_inst1|cnt~12, uart_top, 1
instance = comp, \b2v_inst1|cnt[6] , b2v_inst1|cnt[6], uart_top, 1
instance = comp, \b2v_inst1|Selector5~0 , b2v_inst1|Selector5~0, uart_top, 1
instance = comp, \b2v_inst1|cnt~6 , b2v_inst1|cnt~6, uart_top, 1
instance = comp, \b2v_inst1|cnt[3] , b2v_inst1|cnt[3], uart_top, 1
instance = comp, \b2v_inst1|WideOr10~0 , b2v_inst1|WideOr10~0, uart_top, 1
instance = comp, \b2v_inst1|cnt[0]~7 , b2v_inst1|cnt[0]~7, uart_top, 1
instance = comp, \b2v_inst1|idle~0 , b2v_inst1|idle~0, uart_top, 1
instance = comp, \b2v_inst1|idle , b2v_inst1|idle, uart_top, 1
instance = comp, \rxd~input , rxd~input, uart_top, 1
instance = comp, \b2v_inst1|rxbuf , b2v_inst1|rxbuf, uart_top, 1
instance = comp, \b2v_inst1|rxfall~0 , b2v_inst1|rxfall~0, uart_top, 1
instance = comp, \b2v_inst1|rxfall , b2v_inst1|rxfall, uart_top, 1
instance = comp, \b2v_inst1|Decoder0~0 , b2v_inst1|Decoder0~0, uart_top, 1
instance = comp, \b2v_inst1|Decoder0~1 , b2v_inst1|Decoder0~1, uart_top, 1
instance = comp, \b2v_inst1|Decoder0~2 , b2v_inst1|Decoder0~2, uart_top, 1
instance = comp, \b2v_inst1|receive~0 , b2v_inst1|receive~0, uart_top, 1
instance = comp, \b2v_inst1|receive , b2v_inst1|receive, uart_top, 1
instance = comp, \b2v_inst1|cnt~9 , b2v_inst1|cnt~9, uart_top, 1
instance = comp, \b2v_inst1|cnt[1] , b2v_inst1|cnt[1], uart_top, 1
instance = comp, \b2v_inst1|cnt[0]~0 , b2v_inst1|cnt[0]~0, uart_top, 1
instance = comp, \b2v_inst1|rxd_en~1 , b2v_inst1|rxd_en~1, uart_top, 1
instance = comp, \b2v_inst1|rxd_en~2 , b2v_inst1|rxd_en~2, uart_top, 1
instance = comp, \b2v_inst1|rxd_en~0 , b2v_inst1|rxd_en~0, uart_top, 1
instance = comp, \b2v_inst1|rxd_en~3 , b2v_inst1|rxd_en~3, uart_top, 1
instance = comp, \b2v_inst1|rxd_en , b2v_inst1|rxd_en, uart_top, 1
instance = comp, \b2v_inst1|presult~0 , b2v_inst1|presult~0, uart_top, 1
instance = comp, \b2v_inst1|presult~1 , b2v_inst1|presult~1, uart_top, 1
instance = comp, \b2v_inst1|presult~2 , b2v_inst1|presult~2, uart_top, 1
instance = comp, \b2v_inst1|presult~3 , b2v_inst1|presult~3, uart_top, 1
instance = comp, \b2v_inst1|presult , b2v_inst1|presult, uart_top, 1
instance = comp, \b2v_inst1|rxd_data[7]~0 , b2v_inst1|rxd_data[7]~0, uart_top, 1
instance = comp, \b2v_inst1|dataerror~0 , b2v_inst1|dataerror~0, uart_top, 1
instance = comp, \b2v_inst1|dataerror~1 , b2v_inst1|dataerror~1, uart_top, 1
instance = comp, \b2v_inst1|dataerror , b2v_inst1|dataerror, uart_top, 1
instance = comp, \b2v_inst1|frameerror~0 , b2v_inst1|frameerror~0, uart_top, 1
instance = comp, \b2v_inst1|frameerror , b2v_inst1|frameerror, uart_top, 1
instance = comp, \b2v_inst2|txd_en_buf~feeder , b2v_inst2|txd_en_buf~feeder, uart_top, 1
instance = comp, \b2v_inst2|txd_en_buf , b2v_inst2|txd_en_buf, uart_top, 1
instance = comp, \b2v_inst2|txd_en_rise~0 , b2v_inst2|txd_en_rise~0, uart_top, 1
instance = comp, \b2v_inst2|txd_en_rise , b2v_inst2|txd_en_rise, uart_top, 1
instance = comp, \b2v_inst2|Add0~0 , b2v_inst2|Add0~0, uart_top, 1
instance = comp, \b2v_inst2|cnt~5 , b2v_inst2|cnt~5, uart_top, 1
instance = comp, \b2v_inst2|Equal0~0 , b2v_inst2|Equal0~0, uart_top, 1
instance = comp, \b2v_inst2|cnt~13 , b2v_inst2|cnt~13, uart_top, 1
instance = comp, \b2v_inst2|cnt~15 , b2v_inst2|cnt~15, uart_top, 1
instance = comp, \b2v_inst2|Add0~6 , b2v_inst2|Add0~6, uart_top, 1
instance = comp, \b2v_inst2|Add0~8 , b2v_inst2|Add0~8, uart_top, 1
instance = comp, \b2v_inst2|cnt~10 , b2v_inst2|cnt~10, uart_top, 1
instance = comp, \b2v_inst2|cnt~16 , b2v_inst2|cnt~16, uart_top, 1
instance = comp, \b2v_inst2|cnt[4] , b2v_inst2|cnt[4], uart_top, 1
instance = comp, \b2v_inst2|Add0~10 , b2v_inst2|Add0~10, uart_top, 1
instance = comp, \b2v_inst2|Add0~12 , b2v_inst2|Add0~12, uart_top, 1
instance = comp, \b2v_inst2|cnt~11 , b2v_inst2|cnt~11, uart_top, 1
instance = comp, \b2v_inst2|cnt~12 , b2v_inst2|cnt~12, uart_top, 1
instance = comp, \b2v_inst2|cnt[6] , b2v_inst2|cnt[6], uart_top, 1
instance = comp, \b2v_inst2|Add0~14 , b2v_inst2|Add0~14, uart_top, 1
instance = comp, \b2v_inst2|cnt~14 , b2v_inst2|cnt~14, uart_top, 1
instance = comp, \b2v_inst2|cnt[7] , b2v_inst2|cnt[7], uart_top, 1
instance = comp, \b2v_inst2|cnt[3]~7 , b2v_inst2|cnt[3]~7, uart_top, 1
instance = comp, \b2v_inst2|cnt[3]~6 , b2v_inst2|cnt[3]~6, uart_top, 1
instance = comp, \b2v_inst2|cnt[3]~8 , b2v_inst2|cnt[3]~8, uart_top, 1
instance = comp, \b2v_inst2|cnt~9 , b2v_inst2|cnt~9, uart_top, 1
instance = comp, \b2v_inst2|cnt[5] , b2v_inst2|cnt[5], uart_top, 1
instance = comp, \b2v_inst2|Equal0~1 , b2v_inst2|Equal0~1, uart_top, 1
instance = comp, \b2v_inst2|Selector6~0 , b2v_inst2|Selector6~0, uart_top, 1
instance = comp, \b2v_inst2|cnt[0]~0 , b2v_inst2|cnt[0]~0, uart_top, 1
instance = comp, \b2v_inst2|cnt[0]~1 , b2v_inst2|cnt[0]~1, uart_top, 1
instance = comp, \b2v_inst2|cnt~4 , b2v_inst2|cnt~4, uart_top, 1
instance = comp, \b2v_inst2|cnt[0] , b2v_inst2|cnt[0], uart_top, 1
instance = comp, \b2v_inst2|Add0~2 , b2v_inst2|Add0~2, uart_top, 1
instance = comp, \b2v_inst2|cnt~3 , b2v_inst2|cnt~3, uart_top, 1
instance = comp, \b2v_inst2|cnt[1] , b2v_inst2|cnt[1], uart_top, 1
instance = comp, \b2v_inst2|Add0~4 , b2v_inst2|Add0~4, uart_top, 1
instance = comp, \b2v_inst2|cnt~2 , b2v_inst2|cnt~2, uart_top, 1
instance = comp, \b2v_inst2|cnt[2] , b2v_inst2|cnt[2], uart_top, 1
instance = comp, \b2v_inst2|cnt~17 , b2v_inst2|cnt~17, uart_top, 1
instance = comp, \b2v_inst2|cnt[3] , b2v_inst2|cnt[3], uart_top, 1
instance = comp, \b2v_inst2|Equal0~2 , b2v_inst2|Equal0~2, uart_top, 1
instance = comp, \b2v_inst2|send~0 , b2v_inst2|send~0, uart_top, 1
instance = comp, \b2v_inst2|send , b2v_inst2|send, uart_top, 1
instance = comp, \b2v_inst2|idle~0 , b2v_inst2|idle~0, uart_top, 1
instance = comp, \b2v_inst2|idle~1 , b2v_inst2|idle~1, uart_top, 1
instance = comp, \b2v_inst2|idle , b2v_inst2|idle, uart_top, 1
instance = comp, \b2v_inst1|rxd_data[0]~1 , b2v_inst1|rxd_data[0]~1, uart_top, 1
instance = comp, \b2v_inst1|rxd_data[3]~8 , b2v_inst1|rxd_data[3]~8, uart_top, 1
instance = comp, \b2v_inst1|rxd_data[3]~9 , b2v_inst1|rxd_data[3]~9, uart_top, 1
instance = comp, \b2v_inst1|rxd_data[3] , b2v_inst1|rxd_data[3], uart_top, 1
instance = comp, \b2v_inst1|rxd_data[4]~10 , b2v_inst1|rxd_data[4]~10, uart_top, 1
instance = comp, \b2v_inst1|rxd_data[4]~11 , b2v_inst1|rxd_data[4]~11, uart_top, 1
instance = comp, \b2v_inst1|rxd_data[4] , b2v_inst1|rxd_data[4], uart_top, 1
instance = comp, \b2v_inst1|rxd_data[6]~6 , b2v_inst1|rxd_data[6]~6, uart_top, 1
instance = comp, \b2v_inst1|rxd_data[6]~13 , b2v_inst1|rxd_data[6]~13, uart_top, 1
instance = comp, \b2v_inst1|rxd_data[6] , b2v_inst1|rxd_data[6], uart_top, 1
instance = comp, \b2v_inst2|Selector5~0 , b2v_inst2|Selector5~0, uart_top, 1
instance = comp, \b2v_inst1|rxd_data[1]~4 , b2v_inst1|rxd_data[1]~4, uart_top, 1
instance = comp, \b2v_inst1|rxd_data[5]~12 , b2v_inst1|rxd_data[5]~12, uart_top, 1
instance = comp, \b2v_inst1|rxd_data[5] , b2v_inst1|rxd_data[5], uart_top, 1
instance = comp, \b2v_inst2|Selector5~1 , b2v_inst2|Selector5~1, uart_top, 1
instance = comp, \b2v_inst2|Selector5~2 , b2v_inst2|Selector5~2, uart_top, 1
instance = comp, \b2v_inst2|Selector5~3 , b2v_inst2|Selector5~3, uart_top, 1
instance = comp, \b2v_inst1|rxd_data[0]~2 , b2v_inst1|rxd_data[0]~2, uart_top, 1
instance = comp, \b2v_inst1|rxd_data[0]~3 , b2v_inst1|rxd_data[0]~3, uart_top, 1
instance = comp, \b2v_inst1|rxd_data[0] , b2v_inst1|rxd_data[0], uart_top, 1
instance = comp, \b2v_inst1|rxd_data[1]~5 , b2v_inst1|rxd_data[1]~5, uart_top, 1
instance = comp, \b2v_inst1|rxd_data[1] , b2v_inst1|rxd_data[1], uart_top, 1
instance = comp, \b2v_inst1|rxd_data[2]~7 , b2v_inst1|rxd_data[2]~7, uart_top, 1
instance = comp, \b2v_inst1|rxd_data[2] , b2v_inst1|rxd_data[2], uart_top, 1
instance = comp, \b2v_inst2|Selector5~4 , b2v_inst2|Selector5~4, uart_top, 1
instance = comp, \b2v_inst2|Selector5~5 , b2v_inst2|Selector5~5, uart_top, 1
instance = comp, \b2v_inst2|Selector5~10 , b2v_inst2|Selector5~10, uart_top, 1
instance = comp, \b2v_inst2|Selector5~11 , b2v_inst2|Selector5~11, uart_top, 1
instance = comp, \b2v_inst2|presult~1 , b2v_inst2|presult~1, uart_top, 1
instance = comp, \b2v_inst2|presult~6 , b2v_inst2|presult~6, uart_top, 1
instance = comp, \b2v_inst2|presult~7 , b2v_inst2|presult~7, uart_top, 1
instance = comp, \b2v_inst2|presult~2 , b2v_inst2|presult~2, uart_top, 1
instance = comp, \b2v_inst2|presult~0 , b2v_inst2|presult~0, uart_top, 1
instance = comp, \b2v_inst1|rxd_data[7]~14 , b2v_inst1|rxd_data[7]~14, uart_top, 1
instance = comp, \b2v_inst1|rxd_data[7]~15 , b2v_inst1|rxd_data[7]~15, uart_top, 1
instance = comp, \b2v_inst1|rxd_data[7] , b2v_inst1|rxd_data[7], uart_top, 1
instance = comp, \b2v_inst2|presult~3 , b2v_inst2|presult~3, uart_top, 1
instance = comp, \b2v_inst2|presult~4 , b2v_inst2|presult~4, uart_top, 1
instance = comp, \b2v_inst2|presult~5 , b2v_inst2|presult~5, uart_top, 1
instance = comp, \b2v_inst2|presult , b2v_inst2|presult, uart_top, 1
instance = comp, \b2v_inst2|Selector5~6 , b2v_inst2|Selector5~6, uart_top, 1
instance = comp, \b2v_inst2|Selector5~7 , b2v_inst2|Selector5~7, uart_top, 1
instance = comp, \b2v_inst2|Selector5~8 , b2v_inst2|Selector5~8, uart_top, 1
instance = comp, \b2v_inst2|Selector5~9 , b2v_inst2|Selector5~9, uart_top, 1
instance = comp, \b2v_inst2|txd~0 , b2v_inst2|txd~0, uart_top, 1
instance = comp, \b2v_inst2|txd , b2v_inst2|txd, uart_top, 1