// Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, the Altera Quartus II License Agreement,
// the Altera MegaCore Function License Agreement, or other 
// applicable license agreement, including, without limitation, 
// that your use is for the sole purpose of programming logic 
// devices manufactured by Altera and sold by Altera or its 
// authorized distributors.  Please refer to the applicable 
// agreement for further details.

// PROGRAM		"Quartus II 64-Bit"
// VERSION		"Version 15.0.0 Build 145 04/22/2015 SJ Full Version"
// CREATED		"Thu Dec 10 15:34:07 2020"

module uart_top(
	clk,
	rst,
	rxd,
	clkout,
	en,
	dataerror,
	framerror,
	idle,
	txd,
	data
);


input wire	clk;
input wire	rst;
input wire	rxd;
output wire	clkout;
output wire	en;
output wire	dataerror;
output wire	framerror;
output wire	idle;
output wire	txd;
output wire	[7:0] data;

wire	SYNTHESIZED_WIRE_4;
wire	SYNTHESIZED_WIRE_2;
wire	[7:0] SYNTHESIZED_WIRE_3;

assign	clkout = SYNTHESIZED_WIRE_4;
assign	en = SYNTHESIZED_WIRE_2;
assign	data = SYNTHESIZED_WIRE_3;




clkdiv	b2v_inst(
	.clk(clk),
	.rst(rst),
	.clkout(SYNTHESIZED_WIRE_4));
	defparam	b2v_inst.N = 326;


uartrx	b2v_inst1(
	.clk(SYNTHESIZED_WIRE_4),
	.rst(rst),
	.rxd(rxd),
	.rxd_en(SYNTHESIZED_WIRE_2),
	.dataerror(dataerror),
	.frameerror(framerror),
	.rxd_data(SYNTHESIZED_WIRE_3));
	defparam	b2v_inst1.paritymode = 1'b1;


uarttx	b2v_inst2(
	.clk(SYNTHESIZED_WIRE_4),
	.rst(rst),
	.txd_en(SYNTHESIZED_WIRE_2),
	.txd_data(SYNTHESIZED_WIRE_3),
	.idle(idle),
	.txd(txd));
	defparam	b2v_inst2.paritymode = 1'b1;


endmodule