{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1607576042004 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 15.0.0 Build 145 04/22/2015 SJ Full Version " "Version 15.0.0 Build 145 04/22/2015 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1607576042018 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 10 12:54:01 2020 " "Processing started: Thu Dec 10 12:54:01 2020" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1607576042018 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1607576042018 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off uartrx -c uartrx " "Command: quartus_map --read_settings_files=on --write_settings_files=off uartrx -c uartrx" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1607576042018 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1607576042430 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "uartrx.v 1 1 " "Found 1 design units, including 1 entities, in source file uartrx.v" { { "Info" "ISGN_ENTITY_NAME" "1 uartrx " "Found entity 1: uartrx" {  } { { "uartrx.v" "" { Text "E:/altera/15.0/Project/2020/uartrx/uartrx.v" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1607576052752 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1607576052752 ""}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "rxd_data packed uartrx.v(13) " "Verilog HDL Port Declaration warning at uartrx.v(13): data type declaration for \"rxd_data\" declares packed dimensions but the port declaration declaration does not" {  } { { "uartrx.v" "" { Text "E:/altera/15.0/Project/2020/uartrx/uartrx.v" 13 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "Quartus II" 0 -1 1607576052753 ""}
{ "Info" "IVRFX_HDL_SEE_DECLARATION" "rxd_data uartrx.v(8) " "HDL info at uartrx.v(8): see declaration for object \"rxd_data\"" {  } { { "uartrx.v" "" { Text "E:/altera/15.0/Project/2020/uartrx/uartrx.v" 8 0 0 } }  } 0 10499 "HDL info at %2!s!: see declaration for object \"%1!s!\"" 0 0 "Quartus II" 0 -1 1607576052753 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "uartrx " "Elaborating entity \"uartrx\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1607576052789 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1607576053560 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1607576054102 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1607576054102 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "75 " "Implemented 75 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Implemented 3 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1607576054154 ""} { "Info" "ICUT_CUT_TM_OPINS" "11 " "Implemented 11 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1607576054154 ""} { "Info" "ICUT_CUT_TM_LCELLS" "61 " "Implemented 61 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1607576054154 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1607576054154 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4831 " "Peak virtual memory: 4831 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1607576054186 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 10 12:54:14 2020 " "Processing ended: Thu Dec 10 12:54:14 2020" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1607576054186 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Elapsed time: 00:00:13" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1607576054186 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:24 " "Total CPU time (on all processors): 00:00:24" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1607576054186 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1607576054186 ""}