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// *****************************************************************************
// This file contains a Verilog test bench template that is freely editable to  
// suit user's needs .Comments are provided in each section to help the user    
// fill out necessary details.                                                  
// *****************************************************************************
// Generated on "12/10/2020 09:48:53"
                                                                                
// Verilog Test Bench template for design : uarttx
// 
// Simulation tool : ModelSim (Verilog)
// 

`timescale 1 ps/ 1 ps
module uarttx_vlg_tst();
// constants                                           
// general purpose registers
reg eachvec;
// test vector input registers
reg clk;
reg rst;
reg [7:0] txd_data;
reg txd_en;
// wires                                               
wire idle;
wire txd;

// assign statements (if any)                          
uarttx i1 (
// port map - connection between master ports and signals/registers   
	.clk(clk),
	.idle(idle),
	.rst(rst),
	.txd(txd),
	.txd_data(txd_data),
	.txd_en(txd_en)
);
initial                                                
begin                                                  
// code that executes only once                        
// insert code here --> begin                          
                                                       
// --> end                                             
$display("Running testbench");                       
end                                                    
always                                                 
// optional sensitivity list                           
// @(event1 or event2 or .... eventn)                  
begin                                                  
// code executes for every event on sensitivity list   
// insert code here --> begin                          
                                                       
@eachvec;                                              
// --> end                                             
end                                                    
endmodule