{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1606978527013 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 15.0.0 Build 145 04/22/2015 SJ Full Version " "Version 15.0.0 Build 145 04/22/2015 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1606978527026 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 03 14:55:26 2020 " "Processing started: Thu Dec 03 14:55:26 2020" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1606978527026 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1606978527026 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off add_8 -c add_8 " "Command: quartus_map --read_settings_files=on --write_settings_files=off add_8 -c add_8" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1606978527026 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1606978527512 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "add_1.v 1 1 " "Found 1 design units, including 1 entities, in source file add_1.v" { { "Info" "ISGN_ENTITY_NAME" "1 add_1 " "Found entity 1: add_1" {  } { { "add_1.v" "" { Text "E:/altera/15.0/Project/2020/add_8/add_1.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1606978537446 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1606978537446 ""}
{ "Error" "EVRFX_VERI_MIXED_BY_NAME_BY_ORDER_PORT_CONNECT" "add_8.v(66) " "Verilog HDL Module Instantiation error at add_8.v(66): cannot connect instance ports both by order and by name" {  } { { "add_8.v" "" { Text "E:/altera/15.0/Project/2020/add_8/add_8.v" 66 0 0 } }  } 0 10267 "Verilog HDL Module Instantiation error at %1!s!: cannot connect instance ports both by order and by name" 0 0 "Quartus II" 0 -1 1606978537449 ""}
{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "add_8 add_8.v(1) " "Ignored design unit \"add_8\" at add_8.v(1) due to previous errors" {  } { { "add_8.v" "" { Text "E:/altera/15.0/Project/2020/add_8/add_8.v" 1 0 0 } }  } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Quartus II" 0 -1 1606978537449 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "add_8.v 0 0 " "Found 0 design units, including 0 entities, in source file add_8.v" {  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1606978537449 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "h_add.v 1 1 " "Found 1 design units, including 1 entities, in source file h_add.v" { { "Info" "ISGN_ENTITY_NAME" "1 h_add " "Found entity 1: h_add" {  } { { "h_add.v" "" { Text "E:/altera/15.0/Project/2020/add_8/h_add.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1606978537451 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1606978537451 ""}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 2 errors, 0 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "4779 " "Peak virtual memory: 4779 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1606978537553 ""} { "Error" "EQEXE_END_BANNER_TIME" "Thu Dec 03 14:55:37 2020 " "Processing ended: Thu Dec 03 14:55:37 2020" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1606978537553 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1606978537553 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1606978537553 ""}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1606978537553 ""}
{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 4 s 0 s " "Quartus II Full Compilation was unsuccessful. 4 errors, 0 warnings" {  } {  } 0 293001 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1606978538175 ""}