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// *****************************************************************************
// This file contains a Verilog test bench template that is freely editable to  
// suit user's needs .Comments are provided in each section to help the user    
// fill out necessary details.                                                  
// *****************************************************************************
// Generated on "12/02/2020 21:09:35"
                                                                                
// Verilog Test Bench template for design : h_add
// 
// Simulation tool : ModelSim (Verilog)
// 

`timescale 100ps/10 ps
module h_add_vlg_tst();
reg a,b;
   wire cout,sum;
   h_add i1(cout,sum,a,b);
 	  parameter period1=50,period2=100;
	  parameter pulse=40;

initial   
  begin  
      a=1'b0;
      repeat(pulse)
        #(period1/2) a=~a;
  end
 initial  
  begin
     b=1'b0;
    repeat(pulse)
	  #(period2/2) b=~b;
   end  
endmodule