{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1608148099046 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 15.0.0 Build 145 04/22/2015 SJ Full Version " "Version 15.0.0 Build 145 04/22/2015 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1608148099060 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 17 03:48:18 2020 " "Processing started: Thu Dec 17 03:48:18 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1608148099060 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1608148099060 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off traffic -c traffic " "Command: quartus_map --read_settings_files=on --write_settings_files=off traffic -c traffic" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1608148099060 ""} { "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1608148099484 ""} { "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "traffic_con.v(38) " "Verilog HDL information at traffic_con.v(38): always construct contains both blocking and non-blocking assignments" { } { { "traffic_con.v" "" { Text "E:/altera/15.0/Project/2020/traffic/traffic_con.v" 38 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1608148110552 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "traffic_con.v 1 1 " "Found 1 design units, including 1 entities, in source file traffic_con.v" { { "Info" "ISGN_ENTITY_NAME" "1 traffic_con " "Found entity 1: traffic_con" { } { { "traffic_con.v" "" { Text "E:/altera/15.0/Project/2020/traffic/traffic_con.v" 2 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1608148110555 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1608148110555 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "traffic_top.v 1 1 " "Found 1 design units, including 1 entities, in source file traffic_top.v" { { "Info" "ISGN_ENTITY_NAME" "1 traffic_top " "Found entity 1: traffic_top" { } { { "traffic_top.v" "" { Text "E:/altera/15.0/Project/2020/traffic/traffic_top.v" 2 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1608148110556 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1608148110556 ""} { "Info" "ISGN_START_ELABORATION_TOP" "traffic_top " "Elaborating entity \"traffic_top\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1608148110601 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "traffic_con traffic_con:primary_light " "Elaborating entity \"traffic_con\" for hierarchy \"traffic_con:primary_light\"" { } { { "traffic_top.v" "primary_light" { Text "E:/altera/15.0/Project/2020/traffic/traffic_top.v" 16 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1608148110621 ""} { "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "green_time traffic_con.v(30) " "Verilog HDL Always Construct warning at traffic_con.v(30): variable \"green_time\" is read inside the Always Construct but isn't in the Always Construct's Event Control" { } { { "traffic_con.v" "" { Text "E:/altera/15.0/Project/2020/traffic/traffic_con.v" 30 0 0 } } } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "Quartus II" 0 -1 1608148110622 "|traffic_con"} { "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "yellow_time traffic_con.v(32) " "Verilog HDL Always Construct warning at traffic_con.v(32): variable \"yellow_time\" is read inside the Always Construct but isn't in the Always Construct's Event Control" { } { { "traffic_con.v" "" { Text "E:/altera/15.0/Project/2020/traffic/traffic_con.v" 32 0 0 } } } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "Quartus II" 0 -1 1608148110622 "|traffic_con"} { "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "red_time traffic_con.v(34) " "Verilog HDL Always Construct warning at traffic_con.v(34): variable \"red_time\" is read inside the Always Construct but isn't in the Always Construct's Event Control" { } { { "traffic_con.v" "" { Text "E:/altera/15.0/Project/2020/traffic/traffic_con.v" 34 0 0 } } } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "Quartus II" 0 -1 1608148110622 "|traffic_con"} { "Warning" "WVRFX_L2_VERI_INCOMPLETE_CASE_STATEMENT" "traffic_con.v(28) " "Verilog HDL Case Statement warning at traffic_con.v(28): incomplete case statement has no default case item" { } { { "traffic_con.v" "" { Text "E:/altera/15.0/Project/2020/traffic/traffic_con.v" 28 0 0 } } } 0 10270 "Verilog HDL Case Statement warning at %1!s!: incomplete case statement has no default case item" 0 0 "Quartus II" 0 -1 1608148110623 "|traffic_con"} { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "ticks traffic_con.v(25) " "Verilog HDL Always Construct warning at traffic_con.v(25): inferring latch(es) for variable \"ticks\", which holds its previous value in one or more paths through the always construct" { } { { "traffic_con.v" "" { Text "E:/altera/15.0/Project/2020/traffic/traffic_con.v" 25 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1608148110623 "|traffic_con"} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 traffic_con.v(83) " "Verilog HDL assignment warning at traffic_con.v(83): truncated value with size 32 to match size of target (2)" { } { { "traffic_con.v" "" { Text "E:/altera/15.0/Project/2020/traffic/traffic_con.v" 83 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1608148110623 "|traffic_con"} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 traffic_con.v(87) " "Verilog HDL assignment warning at traffic_con.v(87): truncated value with size 32 to match size of target (8)" { } { { "traffic_con.v" "" { Text "E:/altera/15.0/Project/2020/traffic/traffic_con.v" 87 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1608148110623 "|traffic_con"} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 traffic_con.v(90) " "Verilog HDL assignment warning at traffic_con.v(90): truncated value with size 32 to match size of target (8)" { } { { "traffic_con.v" "" { Text "E:/altera/15.0/Project/2020/traffic/traffic_con.v" 90 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1608148110623 "|traffic_con"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ticks\[0\] traffic_con.v(27) " "Inferred latch for \"ticks\[0\]\" at traffic_con.v(27)" { } { { "traffic_con.v" "" { Text "E:/altera/15.0/Project/2020/traffic/traffic_con.v" 27 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1608148110623 "|traffic_con"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ticks\[1\] traffic_con.v(27) " "Inferred latch for \"ticks\[1\]\" at traffic_con.v(27)" { } { { "traffic_con.v" "" { Text "E:/altera/15.0/Project/2020/traffic/traffic_con.v" 27 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1608148110623 "|traffic_con"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ticks\[2\] traffic_con.v(27) " "Inferred latch for \"ticks\[2\]\" at traffic_con.v(27)" { } { { "traffic_con.v" "" { Text "E:/altera/15.0/Project/2020/traffic/traffic_con.v" 27 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1608148110623 "|traffic_con"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ticks\[3\] traffic_con.v(27) " "Inferred latch for \"ticks\[3\]\" at traffic_con.v(27)" { } { { "traffic_con.v" "" { Text "E:/altera/15.0/Project/2020/traffic/traffic_con.v" 27 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1608148110623 "|traffic_con"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ticks\[4\] traffic_con.v(27) " "Inferred latch for \"ticks\[4\]\" at traffic_con.v(27)" { } { { "traffic_con.v" "" { Text "E:/altera/15.0/Project/2020/traffic/traffic_con.v" 27 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1608148110623 "|traffic_con"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ticks\[5\] traffic_con.v(27) " "Inferred latch for \"ticks\[5\]\" at traffic_con.v(27)" { } { { "traffic_con.v" "" { Text "E:/altera/15.0/Project/2020/traffic/traffic_con.v" 27 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1608148110623 "|traffic_con"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ticks\[6\] traffic_con.v(27) " "Inferred latch for \"ticks\[6\]\" at traffic_con.v(27)" { } { { "traffic_con.v" "" { Text "E:/altera/15.0/Project/2020/traffic/traffic_con.v" 27 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1608148110623 "|traffic_con"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ticks\[7\] traffic_con.v(27) " "Inferred latch for \"ticks\[7\]\" at traffic_con.v(27)" { } { { "traffic_con.v" "" { Text "E:/altera/15.0/Project/2020/traffic/traffic_con.v" 27 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1608148110623 "|traffic_con"} { "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "traffic_con:primary_light\|ticks\[0\] " "Latch traffic_con:primary_light\|ticks\[0\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA traffic_con:primary_light\|s\[1\] " "Ports D and ENA on the latch are fed by the same signal traffic_con:primary_light\|s\[1\]" { } { { "traffic_con.v" "" { Text "E:/altera/15.0/Project/2020/traffic/traffic_con.v" 38 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Quartus II" 0 -1 1608148111175 ""} } { { "traffic_con.v" "" { Text "E:/altera/15.0/Project/2020/traffic/traffic_con.v" 27 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Quartus II" 0 -1 1608148111175 ""} { "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "traffic_con:primary_light\|ticks\[1\] " "Latch traffic_con:primary_light\|ticks\[1\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA traffic_con:primary_light\|s\[1\] " "Ports D and ENA on the latch are fed by the same signal traffic_con:primary_light\|s\[1\]" { } { { "traffic_con.v" "" { Text "E:/altera/15.0/Project/2020/traffic/traffic_con.v" 38 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Quartus II" 0 -1 1608148111175 ""} } { { "traffic_con.v" "" { Text "E:/altera/15.0/Project/2020/traffic/traffic_con.v" 27 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Quartus II" 0 -1 1608148111175 ""} { "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "traffic_con:primary_light\|ticks\[2\] " "Latch traffic_con:primary_light\|ticks\[2\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA traffic_con:primary_light\|s\[1\] " "Ports D and ENA on the latch are fed by the same signal traffic_con:primary_light\|s\[1\]" { } { { "traffic_con.v" "" { Text "E:/altera/15.0/Project/2020/traffic/traffic_con.v" 38 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Quartus II" 0 -1 1608148111176 ""} } { { "traffic_con.v" "" { Text "E:/altera/15.0/Project/2020/traffic/traffic_con.v" 27 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Quartus II" 0 -1 1608148111176 ""} { "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "traffic_con:primary_light\|ticks\[3\] " "Latch traffic_con:primary_light\|ticks\[3\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA traffic_con:primary_light\|s\[1\] " "Ports D and ENA on the latch are fed by the same signal traffic_con:primary_light\|s\[1\]" { } { { "traffic_con.v" "" { Text "E:/altera/15.0/Project/2020/traffic/traffic_con.v" 38 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Quartus II" 0 -1 1608148111176 ""} } { { "traffic_con.v" "" { Text "E:/altera/15.0/Project/2020/traffic/traffic_con.v" 27 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Quartus II" 0 -1 1608148111176 ""} { "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "traffic_con:primary_light\|ticks\[4\] " "Latch traffic_con:primary_light\|ticks\[4\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA traffic_con:primary_light\|s\[1\] " "Ports D and ENA on the latch are fed by the same signal traffic_con:primary_light\|s\[1\]" { } { { "traffic_con.v" "" { Text "E:/altera/15.0/Project/2020/traffic/traffic_con.v" 38 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Quartus II" 0 -1 1608148111176 ""} } { { "traffic_con.v" "" { Text "E:/altera/15.0/Project/2020/traffic/traffic_con.v" 27 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Quartus II" 0 -1 1608148111176 ""} { "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "traffic_con:primary_light\|ticks\[5\] " "Latch traffic_con:primary_light\|ticks\[5\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA traffic_con:primary_light\|s\[1\] " "Ports D and ENA on the latch are fed by the same signal traffic_con:primary_light\|s\[1\]" { } { { "traffic_con.v" "" { Text "E:/altera/15.0/Project/2020/traffic/traffic_con.v" 38 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Quartus II" 0 -1 1608148111176 ""} } { { "traffic_con.v" "" { Text "E:/altera/15.0/Project/2020/traffic/traffic_con.v" 27 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Quartus II" 0 -1 1608148111176 ""} { "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "traffic_con:primary_light\|ticks\[6\] " "Latch traffic_con:primary_light\|ticks\[6\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA traffic_con:primary_light\|s\[1\] " "Ports D and ENA on the latch are fed by the same signal traffic_con:primary_light\|s\[1\]" { } { { "traffic_con.v" "" { Text "E:/altera/15.0/Project/2020/traffic/traffic_con.v" 38 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Quartus II" 0 -1 1608148111177 ""} } { { "traffic_con.v" "" { Text "E:/altera/15.0/Project/2020/traffic/traffic_con.v" 27 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Quartus II" 0 -1 1608148111177 ""} { "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "traffic_con:primary_light\|ticks\[7\] " "Latch traffic_con:primary_light\|ticks\[7\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA traffic_con:primary_light\|s\[1\] " "Ports D and ENA on the latch are fed by the same signal traffic_con:primary_light\|s\[1\]" { } { { "traffic_con.v" "" { Text "E:/altera/15.0/Project/2020/traffic/traffic_con.v" 38 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Quartus II" 0 -1 1608148111177 ""} } { { "traffic_con.v" "" { Text "E:/altera/15.0/Project/2020/traffic/traffic_con.v" 27 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Quartus II" 0 -1 1608148111177 ""} { "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "traffic_con:secondary_light\|ticks\[0\] " "Latch traffic_con:secondary_light\|ticks\[0\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA traffic_con:secondary_light\|s\[0\] " "Ports D and ENA on the latch are fed by the same signal traffic_con:secondary_light\|s\[0\]" { } { { "traffic_con.v" "" { Text "E:/altera/15.0/Project/2020/traffic/traffic_con.v" 38 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Quartus II" 0 -1 1608148111177 ""} } { { "traffic_con.v" "" { Text "E:/altera/15.0/Project/2020/traffic/traffic_con.v" 27 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Quartus II" 0 -1 1608148111177 ""} { "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "traffic_con:secondary_light\|ticks\[1\] " "Latch traffic_con:secondary_light\|ticks\[1\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA traffic_con:secondary_light\|s\[0\] " "Ports D and ENA on the latch are fed by the same signal traffic_con:secondary_light\|s\[0\]" { } { { "traffic_con.v" "" { Text "E:/altera/15.0/Project/2020/traffic/traffic_con.v" 38 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Quartus II" 0 -1 1608148111177 ""} } { { "traffic_con.v" "" { Text "E:/altera/15.0/Project/2020/traffic/traffic_con.v" 27 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Quartus II" 0 -1 1608148111177 ""} { "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "traffic_con:secondary_light\|ticks\[2\] " "Latch traffic_con:secondary_light\|ticks\[2\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA traffic_con:secondary_light\|s\[0\] " "Ports D and ENA on the latch are fed by the same signal traffic_con:secondary_light\|s\[0\]" { } { { "traffic_con.v" "" { Text "E:/altera/15.0/Project/2020/traffic/traffic_con.v" 38 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Quartus II" 0 -1 1608148111178 ""} } { { "traffic_con.v" "" { Text "E:/altera/15.0/Project/2020/traffic/traffic_con.v" 27 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Quartus II" 0 -1 1608148111178 ""} { "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "traffic_con:secondary_light\|ticks\[3\] " "Latch traffic_con:secondary_light\|ticks\[3\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA traffic_con:secondary_light\|s\[0\] " "Ports D and ENA on the latch are fed by the same signal traffic_con:secondary_light\|s\[0\]" { } { { "traffic_con.v" "" { Text "E:/altera/15.0/Project/2020/traffic/traffic_con.v" 38 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Quartus II" 0 -1 1608148111178 ""} } { { "traffic_con.v" "" { Text "E:/altera/15.0/Project/2020/traffic/traffic_con.v" 27 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Quartus II" 0 -1 1608148111178 ""} { "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "traffic_con:secondary_light\|ticks\[4\] " "Latch traffic_con:secondary_light\|ticks\[4\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA traffic_con:secondary_light\|s\[0\] " "Ports D and ENA on the latch are fed by the same signal traffic_con:secondary_light\|s\[0\]" { } { { "traffic_con.v" "" { Text "E:/altera/15.0/Project/2020/traffic/traffic_con.v" 38 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Quartus II" 0 -1 1608148111178 ""} } { { "traffic_con.v" "" { Text "E:/altera/15.0/Project/2020/traffic/traffic_con.v" 27 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Quartus II" 0 -1 1608148111178 ""} { "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "traffic_con:secondary_light\|ticks\[5\] " "Latch traffic_con:secondary_light\|ticks\[5\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA traffic_con:secondary_light\|s\[0\] " "Ports D and ENA on the latch are fed by the same signal traffic_con:secondary_light\|s\[0\]" { } { { "traffic_con.v" "" { Text "E:/altera/15.0/Project/2020/traffic/traffic_con.v" 38 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Quartus II" 0 -1 1608148111179 ""} } { { "traffic_con.v" "" { Text "E:/altera/15.0/Project/2020/traffic/traffic_con.v" 27 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Quartus II" 0 -1 1608148111179 ""} { "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "traffic_con:secondary_light\|ticks\[6\] " "Latch traffic_con:secondary_light\|ticks\[6\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA traffic_con:secondary_light\|s\[0\] " "Ports D and ENA on the latch are fed by the same signal traffic_con:secondary_light\|s\[0\]" { } { { "traffic_con.v" "" { Text "E:/altera/15.0/Project/2020/traffic/traffic_con.v" 38 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Quartus II" 0 -1 1608148111179 ""} } { { "traffic_con.v" "" { Text "E:/altera/15.0/Project/2020/traffic/traffic_con.v" 27 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Quartus II" 0 -1 1608148111179 ""} { "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "traffic_con:secondary_light\|ticks\[7\] " "Latch traffic_con:secondary_light\|ticks\[7\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA traffic_con:secondary_light\|s\[0\] " "Ports D and ENA on the latch are fed by the same signal traffic_con:secondary_light\|s\[0\]" { } { { "traffic_con.v" "" { Text "E:/altera/15.0/Project/2020/traffic/traffic_con.v" 38 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Quartus II" 0 -1 1608148111179 ""} } { { "traffic_con.v" "" { Text "E:/altera/15.0/Project/2020/traffic/traffic_con.v" 27 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Quartus II" 0 -1 1608148111179 ""} { "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1608148111320 ""} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "10 " "10 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1608148111737 ""} { "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/altera/15.0/Project/2020/traffic/output_files/traffic.map.smsg " "Generated suppressed messages file E:/altera/15.0/Project/2020/traffic/output_files/traffic.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1608148111784 ""} { "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1608148111951 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1608148111951 ""} { "Info" "ICUT_CUT_TM_SUMMARY" "202 " "Implemented 202 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1608148112035 ""} { "Info" "ICUT_CUT_TM_OPINS" "22 " "Implemented 22 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1608148112035 ""} { "Info" "ICUT_CUT_TM_LCELLS" "152 " "Implemented 152 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1608148112035 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1608148112035 ""} { "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 40 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 40 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4830 " "Peak virtual memory: 4830 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1608148112104 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 17 03:48:32 2020 " "Processing ended: Thu Dec 17 03:48:32 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1608148112104 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:14 " "Elapsed time: 00:00:14" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1608148112104 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:24 " "Total CPU time (on all processors): 00:00:24" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1608148112104 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1608148112104 ""}