//凌智城 201806061211 通信工程1803
`timescale 1 ps/ 1 ps
module traffic_con_vlg_tst();
// constants                                           
// test vector input registers
reg clk;
reg emergency;
reg [7:0] green_time;
reg prim_flag;
reg [7:0] red_time;
reg rst_n;
reg test;
reg [7:0] yellow_time;
// wires                                               
wire [2:0]  ryg_light;
wire [7:0]  wait_time;

// assign statements (if any)                          
traffic_con i1 (
// port map - connection between master ports and signals/registers   
	.clk(clk),
	.emergency(emergency),
	.green_time(green_time),
	.prim_flag(prim_flag),
	.red_time(red_time),
	.rst_n(rst_n),
	.ryg_light(ryg_light),
	.test(test),
	.wait_time(wait_time),
	.yellow_time(yellow_time)
);

always
	begin
		#5 clk=1'b1;
		#5 clk=1'b0;
	end 

initial 
begin
	clk <= 0;
	rst_n <= 0;
	emergency <= 0;
	test <= 0;
	prim_flag <= 1;
	red_time <= 9;
	green_time <= 6;
	yellow_time <= 2;
	#20 rst_n<=1;
	#350 
	begin
		rst_n<=0;
		prim_flag <= 0;
	end
	#20 rst_n<=1;
	#350 
	begin
		red_time <= 12;
		green_time <= 8;
		yellow_time <= 4;
	end
	#350	emergency<=1;
	#350	
	begin
		emergency<=0;
		test<=1;
	end
end  
                                             
endmodule