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// *****************************************************************************
// This file contains a Verilog test bench template that is freely editable to  
// suit user's needs .Comments are provided in each section to help the user    
// fill out necessary details.                                                  
// *****************************************************************************
// Generated on "12/16/2020 22:34:35"
                                                                                
// Verilog Test Bench template for design : traffic_con
// 
// Simulation tool : ModelSim (Verilog)
// 

`timescale 1 ps/ 1 ps
module traffic_con_vlg_tst();
// constants                                           
// general purpose registers
reg eachvec;
// test vector input registers
reg clk;
reg emergency;
reg [7:0] green_time;
reg prim_flag;
reg [7:0] red_time;
reg rst_n;
reg test;
reg [7:0] yellow_time;
// wires                                               
wire [2:0]  ryg_light;
wire [7:0]  wait_time;

// assign statements (if any)                          
traffic_con i1 (
// port map - connection between master ports and signals/registers   
	.clk(clk),
	.emergency(emergency),
	.green_time(green_time),
	.prim_flag(prim_flag),
	.red_time(red_time),
	.rst_n(rst_n),
	.ryg_light(ryg_light),
	.test(test),
	.wait_time(wait_time),
	.yellow_time(yellow_time)
);
initial                                                
begin                                                  
// code that executes only once                        
// insert code here --> begin                          
                                                       
// --> end                                             
$display("Running testbench");                       
end                                                    
always                                                 
// optional sensitivity list                           
// @(event1 or event2 or .... eventn)                  
begin                                                  
// code executes for every event on sensitivity list   
// insert code here --> begin                          
                                                       
@eachvec;                                              
// --> end                                             
end                                                    
endmodule