//凌智城 201806061211 通信工程1803
`timescale 1 ps/ 1 ps
module traffic_top_vlg_tst();
// constants                                           
// test vector input registers
reg clk;
reg emergency;
reg [7:0] prim_green_time;
reg [7:0] prim_red_time;
reg [7:0] prim_yellow_time;
reg rst_n;
reg test;
// wires                                               
wire [2:0]  prim_ryg_light;
wire [7:0]  prim_wait_time;
wire [2:0]  seco_ryg_light;
wire [7:0]  seco_wait_time;

// assign statements (if any)                          
traffic_top i1 (
// port map - connection between master ports and signals/registers   
	.clk(clk),
	.emergency(emergency),
	.prim_green_time(prim_green_time),
	.prim_red_time(prim_red_time),
	.prim_ryg_light(prim_ryg_light),
	.prim_wait_time(prim_wait_time),
	.prim_yellow_time(prim_yellow_time),
	.rst_n(rst_n),
	.seco_ryg_light(seco_ryg_light),
	.seco_wait_time(seco_wait_time),
	.test(test)
);
always
	begin
		#5 clk=1'b1;
		#5 clk=1'b0;
	end 

initial 
begin
	clk <= 0;
	rst_n <= 0;
	emergency <= 0;
	test <= 0;
	prim_red_time <= 6;
	prim_green_time <= 9;
	prim_yellow_time <= 2;
	#20 rst_n<=1;
end                                                    
endmodule