{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1594625494687 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 15.0.0 Build 145 04/22/2015 SJ Full Version " "Version 15.0.0 Build 145 04/22/2015 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1594625494697 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jul 13 15:31:34 2020 " "Processing started: Mon Jul 13 15:31:34 2020" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1594625494697 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1594625494697 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off FMETER -c FMETER " "Command: quartus_map --read_settings_files=on --write_settings_files=off FMETER -c FMETER" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1594625494697 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1594625495047 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "control.vhd 2 1 " "Found 2 design units, including 1 entities, in source file control.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 control-behav " "Found design unit 1: control-behav" {  } { { "control.vhd" "" { Text "E:/altera/15.0/Project/FMETER/control.vhd" 10 -1 0 } }  } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1594625504510 ""} { "Info" "ISGN_ENTITY_NAME" "1 control " "Found entity 1: control" {  } { { "control.vhd" "" { Text "E:/altera/15.0/Project/FMETER/control.vhd" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1594625504510 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1594625504510 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cnt10.vhd 2 1 " "Found 2 design units, including 1 entities, in source file cnt10.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 CNT10-one " "Found design unit 1: CNT10-one" {  } { { "CNT10.vhd" "" { Text "E:/altera/15.0/Project/FMETER/CNT10.vhd" 11 -1 0 } }  } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1594625504510 ""} { "Info" "ISGN_ENTITY_NAME" "1 CNT10 " "Found entity 1: CNT10" {  } { { "CNT10.vhd" "" { Text "E:/altera/15.0/Project/FMETER/CNT10.vhd" 5 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1594625504510 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1594625504510 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "latch4.vhd 2 1 " "Found 2 design units, including 1 entities, in source file latch4.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 LATCH4-one " "Found design unit 1: LATCH4-one" {  } { { "LATCH4.vhd" "" { Text "E:/altera/15.0/Project/FMETER/LATCH4.vhd" 13 -1 0 } }  } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1594625504510 ""} { "Info" "ISGN_ENTITY_NAME" "1 LATCH4 " "Found entity 1: LATCH4" {  } { { "LATCH4.vhd" "" { Text "E:/altera/15.0/Project/FMETER/LATCH4.vhd" 5 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1594625504510 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1594625504510 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "led7s.vhd 2 1 " "Found 2 design units, including 1 entities, in source file led7s.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 LED7S-one " "Found design unit 1: LED7S-one" {  } { { "LED7S.vhd" "" { Text "E:/altera/15.0/Project/FMETER/LED7S.vhd" 10 -1 0 } }  } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1594625504510 ""} { "Info" "ISGN_ENTITY_NAME" "1 LED7S " "Found entity 1: LED7S" {  } { { "LED7S.vhd" "" { Text "E:/altera/15.0/Project/FMETER/LED7S.vhd" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1594625504510 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1594625504510 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fmeter.bdf 1 1 " "Found 1 design units, including 1 entities, in source file fmeter.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 FMETER " "Found entity 1: FMETER" {  } { { "FMETER.bdf" "" { Schematic "E:/altera/15.0/Project/FMETER/FMETER.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1594625504520 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1594625504520 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "LATCH4 " "Elaborating entity \"LATCH4\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1594625504600 ""}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "q LATCH4.vhd(15) " "VHDL Process Statement warning at LATCH4.vhd(15): inferring latch(es) for signal or variable \"q\", which holds its previous value in one or more paths through the process" {  } { { "LATCH4.vhd" "" { Text "E:/altera/15.0/Project/FMETER/LATCH4.vhd" 15 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "Quartus II" 0 -1 1594625504600 "|LATCH4"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "q\[0\] LATCH4.vhd(15) " "Inferred latch for \"q\[0\]\" at LATCH4.vhd(15)" {  } { { "LATCH4.vhd" "" { Text "E:/altera/15.0/Project/FMETER/LATCH4.vhd" 15 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1594625504600 "|LATCH4"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "q\[1\] LATCH4.vhd(15) " "Inferred latch for \"q\[1\]\" at LATCH4.vhd(15)" {  } { { "LATCH4.vhd" "" { Text "E:/altera/15.0/Project/FMETER/LATCH4.vhd" 15 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1594625504600 "|LATCH4"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "q\[2\] LATCH4.vhd(15) " "Inferred latch for \"q\[2\]\" at LATCH4.vhd(15)" {  } { { "LATCH4.vhd" "" { Text "E:/altera/15.0/Project/FMETER/LATCH4.vhd" 15 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1594625504600 "|LATCH4"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "q\[3\] LATCH4.vhd(15) " "Inferred latch for \"q\[3\]\" at LATCH4.vhd(15)" {  } { { "LATCH4.vhd" "" { Text "E:/altera/15.0/Project/FMETER/LATCH4.vhd" 15 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1594625504600 "|LATCH4"}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1594625505399 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1594625506009 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1594625506009 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "13 " "Implemented 13 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1594625506079 ""} { "Info" "ICUT_CUT_TM_OPINS" "4 " "Implemented 4 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1594625506079 ""} { "Info" "ICUT_CUT_TM_LCELLS" "4 " "Implemented 4 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1594625506079 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1594625506079 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4842 " "Peak virtual memory: 4842 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1594625506179 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Jul 13 15:31:46 2020 " "Processing ended: Mon Jul 13 15:31:46 2020" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1594625506179 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Elapsed time: 00:00:12" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1594625506179 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:23 " "Total CPU time (on all processors): 00:00:23" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1594625506179 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1594625506179 ""}