{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1594625188150 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 15.0.0 Build 145 04/22/2015 SJ Full Version " "Version 15.0.0 Build 145 04/22/2015 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1594625188160 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jul 13 15:26:27 2020 " "Processing started: Mon Jul 13 15:26:27 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1594625188160 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1594625188160 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off FMETER -c FMETER " "Command: quartus_map --read_settings_files=on --write_settings_files=off FMETER -c FMETER" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1594625188160 ""} { "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1594625188790 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "control.vhd 2 1 " "Found 2 design units, including 1 entities, in source file control.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 control-behav " "Found design unit 1: control-behav" { } { { "control.vhd" "" { Text "E:/altera/15.0/Project/FMETER/control.vhd" 10 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1594625199836 ""} { "Info" "ISGN_ENTITY_NAME" "1 control " "Found entity 1: control" { } { { "control.vhd" "" { Text "E:/altera/15.0/Project/FMETER/control.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1594625199836 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1594625199836 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cnt10.vhd 2 1 " "Found 2 design units, including 1 entities, in source file cnt10.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 CNT10-one " "Found design unit 1: CNT10-one" { } { { "CNT10.vhd" "" { Text "E:/altera/15.0/Project/FMETER/CNT10.vhd" 11 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1594625199846 ""} { "Info" "ISGN_ENTITY_NAME" "1 CNT10 " "Found entity 1: CNT10" { } { { "CNT10.vhd" "" { Text "E:/altera/15.0/Project/FMETER/CNT10.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1594625199846 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1594625199846 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "latch4.vhd 2 1 " "Found 2 design units, including 1 entities, in source file latch4.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 LATCH4-one " "Found design unit 1: LATCH4-one" { } { { "LATCH4.vhd" "" { Text "E:/altera/15.0/Project/FMETER/LATCH4.vhd" 13 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1594625199846 ""} { "Info" "ISGN_ENTITY_NAME" "1 LATCH4 " "Found entity 1: LATCH4" { } { { "LATCH4.vhd" "" { Text "E:/altera/15.0/Project/FMETER/LATCH4.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1594625199846 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1594625199846 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "led7s.vhd 2 1 " "Found 2 design units, including 1 entities, in source file led7s.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 LED7S-one " "Found design unit 1: LED7S-one" { } { { "LED7S.vhd" "" { Text "E:/altera/15.0/Project/FMETER/LED7S.vhd" 10 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1594625199856 ""} { "Info" "ISGN_ENTITY_NAME" "1 LED7S " "Found entity 1: LED7S" { } { { "LED7S.vhd" "" { Text "E:/altera/15.0/Project/FMETER/LED7S.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1594625199856 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1594625199856 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fmeter.bdf 1 1 " "Found 1 design units, including 1 entities, in source file fmeter.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 FMETER " "Found entity 1: FMETER" { } { { "FMETER.bdf" "" { Schematic "E:/altera/15.0/Project/FMETER/FMETER.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1594625199866 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1594625199866 ""} { "Info" "ISGN_START_ELABORATION_TOP" "LATCH4 " "Elaborating entity \"LATCH4\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1594625199926 ""} { "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "q LATCH4.vhd(15) " "VHDL Process Statement warning at LATCH4.vhd(15): inferring latch(es) for signal or variable \"q\", which holds its previous value in one or more paths through the process" { } { { "LATCH4.vhd" "" { Text "E:/altera/15.0/Project/FMETER/LATCH4.vhd" 15 0 0 } } } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "Quartus II" 0 -1 1594625199946 "|LATCH4"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "q\[0\] LATCH4.vhd(15) " "Inferred latch for \"q\[0\]\" at LATCH4.vhd(15)" { } { { "LATCH4.vhd" "" { Text "E:/altera/15.0/Project/FMETER/LATCH4.vhd" 15 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1594625199946 "|LATCH4"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "q\[1\] LATCH4.vhd(15) " "Inferred latch for \"q\[1\]\" at LATCH4.vhd(15)" { } { { "LATCH4.vhd" "" { Text "E:/altera/15.0/Project/FMETER/LATCH4.vhd" 15 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1594625199946 "|LATCH4"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "q\[2\] LATCH4.vhd(15) " "Inferred latch for \"q\[2\]\" at LATCH4.vhd(15)" { } { { "LATCH4.vhd" "" { Text "E:/altera/15.0/Project/FMETER/LATCH4.vhd" 15 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1594625199946 "|LATCH4"} { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "q\[3\] LATCH4.vhd(15) " "Inferred latch for \"q\[3\]\" at LATCH4.vhd(15)" { } { { "LATCH4.vhd" "" { Text "E:/altera/15.0/Project/FMETER/LATCH4.vhd" 15 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1594625199946 "|LATCH4"} { "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1594625200615 ""} { "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1594625201425 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1594625201425 ""} { "Info" "ICUT_CUT_TM_SUMMARY" "13 " "Implemented 13 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1594625202404 ""} { "Info" "ICUT_CUT_TM_OPINS" "4 " "Implemented 4 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1594625202404 ""} { "Info" "ICUT_CUT_TM_LCELLS" "4 " "Implemented 4 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1594625202404 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1594625202404 ""} { "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4843 " "Peak virtual memory: 4843 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1594625202484 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Jul 13 15:26:42 2020 " "Processing ended: Mon Jul 13 15:26:42 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1594625202484 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:15 " "Elapsed time: 00:00:15" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1594625202484 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:25 " "Total CPU time (on all processors): 00:00:25" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1594625202484 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1594625202484 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1594625207232 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 15.0.0 Build 145 04/22/2015 SJ Full Version " "Version 15.0.0 Build 145 04/22/2015 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1594625207242 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jul 13 15:26:45 2020 " "Processing started: Mon Jul 13 15:26:45 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1594625207242 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1594625207242 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off FMETER -c FMETER " "Command: quartus_fit --read_settings_files=off --write_settings_files=off FMETER -c FMETER" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1594625207242 ""} { "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1594625207492 ""} { "Info" "0" "" "Project = FMETER" { } { } 0 0 "Project = FMETER" 0 0 "Fitter" 0 0 1594625207492 ""} { "Info" "0" "" "Revision = FMETER" { } { } 0 0 "Revision = FMETER" 0 0 "Fitter" 0 0 1594625207492 ""} { "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1594625207692 ""} { "Info" "IMPP_MPP_USER_DEVICE" "FMETER EP4CE6E22C8 " "Selected device EP4CE6E22C8 for design \"FMETER\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1594625207742 ""} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1594625207812 ""} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1594625207812 ""} { "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1594625208152 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10E22C8 " "Device EP4CE10E22C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1594625208491 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15E22C8 " "Device EP4CE15E22C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1594625208491 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE22E22C8 " "Device EP4CE22E22C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1594625208491 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1594625208491 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ 6 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location 6" { } { { "e:/altera/15.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/altera/15.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "E:/altera/15.0/Project/FMETER/" { { 0 { 0 ""} 0 60 9698 10655 0 0 ""} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1594625208491 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ 8 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location 8" { } { { "e:/altera/15.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/altera/15.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "E:/altera/15.0/Project/FMETER/" { { 0 { 0 ""} 0 62 9698 10655 0 0 ""} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1594625208491 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ 12 " "Pin ~ALTERA_DCLK~ is reserved at location 12" { } { { "e:/altera/15.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/altera/15.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "E:/altera/15.0/Project/FMETER/" { { 0 { 0 ""} 0 64 9698 10655 0 0 ""} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1594625208491 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ 13 " "Pin ~ALTERA_DATA0~ is reserved at location 13" { } { { "e:/altera/15.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/altera/15.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "E:/altera/15.0/Project/FMETER/" { { 0 { 0 ""} 0 66 9698 10655 0 0 ""} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1594625208491 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ 101 " "Pin ~ALTERA_nCEO~ is reserved at location 101" { } { { "e:/altera/15.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/altera/15.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "E:/altera/15.0/Project/FMETER/" { { 0 { 0 ""} 0 68 9698 10655 0 0 ""} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1594625208491 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1594625208491 ""} { "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1594625208491 ""} { "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "5 9 " "No exact pin location assignment(s) for 5 pins of 9 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1594625208791 ""} { "Warning" "WTDB_ANALYZE_COMB_LATCHES" "4 " "TimeQuest Timing Analyzer is analyzing 4 combinational loops as latches." { } { } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches." 0 0 "Fitter" 0 -1 1594625209061 ""} { "Critical Warning" "WSTA_SDC_NOT_FOUND" "FMETER.sdc " "Synopsys Design Constraints File file not found: 'FMETER.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1594625209061 ""} { "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1594625209061 ""} { "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1594625209061 ""} { "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1594625209071 ""} { "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1594625209071 ""} { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "le~input (placed in PIN 23 (CLK1, DIFFCLK_0n)) " "Automatically promoted node le~input (placed in PIN 23 (CLK1, DIFFCLK_0n))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1594625209081 ""} } { { "LATCH4.vhd" "" { Text "E:/altera/15.0/Project/FMETER/LATCH4.vhd" 7 0 0 } } { "temporary_test_loc" "" { Generic "E:/altera/15.0/Project/FMETER/" { { 0 { 0 ""} 0 52 9698 10655 0 0 ""} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1594625209081 ""} { "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1594625209521 ""} { "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1594625209521 ""} { "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1594625209521 ""} { "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1594625209521 ""} { "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1594625209521 ""} { "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1594625209521 ""} { "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1594625209521 ""} { "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1594625209521 ""} { "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1594625209521 ""} { "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1594625209521 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1594625209521 ""} { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "4 unused 2.5V 0 4 0 " "Number of I/O pins in group: 4 (unused VREF, 2.5V VCCIO, 0 input, 4 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1594625209521 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1594625209521 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1594625209521 ""} { "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 8 3 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 8 total pin(s) used -- 3 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1594625209521 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 8 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 8 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1594625209521 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 11 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 11 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1594625209521 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 14 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 14 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1594625209521 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 13 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 13 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1594625209521 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 9 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 9 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1594625209521 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 13 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 13 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1594625209521 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 1 11 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 11 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1594625209521 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1594625209521 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1594625209521 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "A\[0\] " "Node \"A\[0\]\" is assigned to location or region, but does not exist in design" { } { { "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "A\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1594625209541 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "A\[1\] " "Node \"A\[1\]\" is assigned to location or region, but does not exist in design" { } { { "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "A\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1594625209541 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "A\[2\] " "Node \"A\[2\]\" is assigned to location or region, but does not exist in design" { } { { "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "A\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1594625209541 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "A\[3\] " "Node \"A\[3\]\" is assigned to location or region, but does not exist in design" { } { { "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "A\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1594625209541 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "A\[4\] " "Node \"A\[4\]\" is assigned to location or region, but does not exist in design" { } { { "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "A\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1594625209541 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "A\[5\] " "Node \"A\[5\]\" is assigned to location or region, but does not exist in design" { } { { "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "A\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1594625209541 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "A\[6\] " "Node \"A\[6\]\" is assigned to location or region, but does not exist in design" { } { { "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "A\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1594625209541 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "B\[0\] " "Node \"B\[0\]\" is assigned to location or region, but does not exist in design" { } { { "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "B\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1594625209541 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "B\[1\] " "Node \"B\[1\]\" is assigned to location or region, but does not exist in design" { } { { "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "B\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1594625209541 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "B\[2\] " "Node \"B\[2\]\" is assigned to location or region, but does not exist in design" { } { { "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "B\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1594625209541 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "B\[3\] " "Node \"B\[3\]\" is assigned to location or region, but does not exist in design" { } { { "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "B\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1594625209541 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "B\[4\] " "Node \"B\[4\]\" is assigned to location or region, but does not exist in design" { } { { "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "B\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1594625209541 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "B\[5\] " "Node \"B\[5\]\" is assigned to location or region, but does not exist in design" { } { { "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "B\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1594625209541 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "B\[6\] " "Node \"B\[6\]\" is assigned to location or region, but does not exist in design" { } { { "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "B\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1594625209541 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLK1 " "Node \"CLK1\" is assigned to location or region, but does not exist in design" { } { { "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLK1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1594625209541 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLKIN " "Node \"CLKIN\" is assigned to location or region, but does not exist in design" { } { { "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLKIN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1594625209541 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "C\[0\] " "Node \"C\[0\]\" is assigned to location or region, but does not exist in design" { } { { "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "C\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1594625209541 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "C\[1\] " "Node \"C\[1\]\" is assigned to location or region, but does not exist in design" { } { { "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "C\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1594625209541 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "C\[2\] " "Node \"C\[2\]\" is assigned to location or region, but does not exist in design" { } { { "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "C\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1594625209541 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "C\[3\] " "Node \"C\[3\]\" is assigned to location or region, but does not exist in design" { } { { "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "C\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1594625209541 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "C\[4\] " "Node \"C\[4\]\" is assigned to location or region, but does not exist in design" { } { { "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "C\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1594625209541 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "C\[5\] " "Node \"C\[5\]\" is assigned to location or region, but does not exist in design" { } { { "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "C\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1594625209541 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "C\[6\] " "Node \"C\[6\]\" is assigned to location or region, but does not exist in design" { } { { "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "C\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1594625209541 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "D\[4\] " "Node \"D\[4\]\" is assigned to location or region, but does not exist in design" { } { { "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "D\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1594625209541 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "D\[5\] " "Node \"D\[5\]\" is assigned to location or region, but does not exist in design" { } { { "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "D\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1594625209541 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "D\[6\] " "Node \"D\[6\]\" is assigned to location or region, but does not exist in design" { } { { "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "e:/altera/15.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "D\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1594625209541 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1594625209541 ""} { "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1594625209541 ""} { "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1594625209551 ""} { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1594625210220 ""} { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1594625210250 ""} { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1594625210260 ""} { "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1594625210370 ""} { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1594625210370 ""} { "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1594625210680 ""} { "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y12 X10_Y24 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y12 to location X10_Y24" { } { { "loc" "" { Generic "E:/altera/15.0/Project/FMETER/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y12 to location X10_Y24"} { { 12 { 0 ""} 0 12 11 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1594625211030 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1594625211030 ""} { "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1594625211070 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1594625211070 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Quartus II" 0 -1 1594625211070 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1594625211070 ""} { "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.05 " "Total time spent on timing analysis during the Fitter is 0.05 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1594625211080 ""} { "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1594625211140 ""} { "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1594625211310 ""} { "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1594625211370 ""} { "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1594625211550 ""} { "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1594625211880 ""} { "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1594625212119 ""} { "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/altera/15.0/Project/FMETER/output_files/FMETER.fit.smsg " "Generated suppressed messages file E:/altera/15.0/Project/FMETER/output_files/FMETER.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1594625212199 ""} { "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 32 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 32 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5610 " "Peak virtual memory: 5610 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1594625212909 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Jul 13 15:26:52 2020 " "Processing ended: Mon Jul 13 15:26:52 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1594625212909 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1594625212909 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1594625212909 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1594625212909 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1594625216507 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 15.0.0 Build 145 04/22/2015 SJ Full Version " "Version 15.0.0 Build 145 04/22/2015 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1594625216517 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jul 13 15:26:56 2020 " "Processing started: Mon Jul 13 15:26:56 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1594625216517 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1594625216517 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off FMETER -c FMETER " "Command: quartus_asm --read_settings_files=off --write_settings_files=off FMETER -c FMETER" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1594625216517 ""} { "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1594625217257 ""} { "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1594625217287 ""} { "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4741 " "Peak virtual memory: 4741 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1594625217626 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Jul 13 15:26:57 2020 " "Processing ended: Mon Jul 13 15:26:57 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1594625217626 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1594625217626 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1594625217626 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1594625217626 ""} { "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1594625218346 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1594625220575 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 15.0.0 Build 145 04/22/2015 SJ Full Version " "Version 15.0.0 Build 145 04/22/2015 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1594625220585 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jul 13 15:27:00 2020 " "Processing started: Mon Jul 13 15:27:00 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1594625220585 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1594625220585 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta FMETER -c FMETER " "Command: quartus_sta FMETER -c FMETER" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1594625220585 ""} { "Info" "0" "" "qsta_default_script.tcl version: #11" { } { } 0 0 "qsta_default_script.tcl version: #11" 0 0 "Quartus II" 0 0 1594625220965 ""} { "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1594625221115 ""} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1594625221175 ""} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1594625221175 ""} { "Warning" "WTDB_ANALYZE_COMB_LATCHES" "4 " "TimeQuest Timing Analyzer is analyzing 4 combinational loops as latches." { } { } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches." 0 0 "Quartus II" 0 -1 1594625221374 ""} { "Critical Warning" "WSTA_SDC_NOT_FOUND" "FMETER.sdc " "Synopsys Design Constraints File file not found: 'FMETER.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1594625221474 ""} { "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1594625221484 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name le le " "create_clock -period 1.000 -name le le" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1594625221484 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1594625221484 ""} { "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1594625221484 ""} { "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1594625221484 ""} { "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1594625221484 ""} { "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1594625221514 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1594625221524 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1594625221544 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1594625221563 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1594625221577 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1594625221581 ""} { "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1594625221591 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1594625221591 ""} { "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1594625221591 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1594625221591 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -3.000 le " " -3.000 -3.000 le " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1594625221591 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1594625221591 ""} { "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1594625221651 ""} { "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1594625221671 ""} { "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1594625221961 ""} { "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1594625222051 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1594625222051 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1594625222071 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1594625222081 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1594625222091 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1594625222101 ""} { "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1594625222101 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1594625222101 ""} { "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1594625222111 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1594625222111 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -3.000 le " " -3.000 -3.000 le " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1594625222111 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1594625222111 ""} { "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1594625222161 ""} { "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1594625222360 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1594625222370 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1594625222380 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1594625222390 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1594625222410 ""} { "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1594625222410 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1594625222410 ""} { "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1594625222420 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1594625222420 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -3.000 le " " -3.000 -3.000 le " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1594625222420 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1594625222420 ""} { "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1594625222860 ""} { "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1594625222860 ""} { "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4863 " "Peak virtual memory: 4863 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1594625223000 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Jul 13 15:27:03 2020 " "Processing ended: Mon Jul 13 15:27:03 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1594625223000 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1594625223000 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1594625223000 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1594625223000 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1594625225349 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 64-Bit " "Running Quartus II 64-Bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 15.0.0 Build 145 04/22/2015 SJ Full Version " "Version 15.0.0 Build 145 04/22/2015 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1594625225359 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jul 13 15:27:05 2020 " "Processing started: Mon Jul 13 15:27:05 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1594625225359 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1594625225359 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off FMETER -c FMETER " "Command: quartus_eda --read_settings_files=off --write_settings_files=off FMETER -c FMETER" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1594625225359 ""} { "Info" "IWSC_DONE_HDL_GENERATION" "FMETER_8_1200mv_85c_slow.vho E:/altera/15.0/Project/FMETER/simulation/modelsim/ simulation " "Generated file FMETER_8_1200mv_85c_slow.vho in folder \"E:/altera/15.0/Project/FMETER/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1594625225899 ""} { "Info" "IWSC_DONE_HDL_GENERATION" "FMETER_8_1200mv_0c_slow.vho E:/altera/15.0/Project/FMETER/simulation/modelsim/ simulation " "Generated file FMETER_8_1200mv_0c_slow.vho in folder \"E:/altera/15.0/Project/FMETER/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1594625225909 ""} { "Info" "IWSC_DONE_HDL_GENERATION" "FMETER_min_1200mv_0c_fast.vho E:/altera/15.0/Project/FMETER/simulation/modelsim/ simulation " "Generated file FMETER_min_1200mv_0c_fast.vho in folder \"E:/altera/15.0/Project/FMETER/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1594625225929 ""} { "Info" "IWSC_DONE_HDL_GENERATION" "FMETER.vho E:/altera/15.0/Project/FMETER/simulation/modelsim/ simulation " "Generated file FMETER.vho in folder \"E:/altera/15.0/Project/FMETER/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1594625225949 ""} { "Info" "IWSC_DONE_HDL_GENERATION" "FMETER_8_1200mv_85c_vhd_slow.sdo E:/altera/15.0/Project/FMETER/simulation/modelsim/ simulation " "Generated file FMETER_8_1200mv_85c_vhd_slow.sdo in folder \"E:/altera/15.0/Project/FMETER/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1594625225969 ""} { "Info" "IWSC_DONE_HDL_GENERATION" "FMETER_8_1200mv_0c_vhd_slow.sdo E:/altera/15.0/Project/FMETER/simulation/modelsim/ simulation " "Generated file FMETER_8_1200mv_0c_vhd_slow.sdo in folder \"E:/altera/15.0/Project/FMETER/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1594625225998 ""} { "Info" "IWSC_DONE_HDL_GENERATION" "FMETER_min_1200mv_0c_vhd_fast.sdo E:/altera/15.0/Project/FMETER/simulation/modelsim/ simulation " "Generated file FMETER_min_1200mv_0c_vhd_fast.sdo in folder \"E:/altera/15.0/Project/FMETER/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1594625226018 ""} { "Info" "IWSC_DONE_HDL_GENERATION" "FMETER_vhd.sdo E:/altera/15.0/Project/FMETER/simulation/modelsim/ simulation " "Generated file FMETER_vhd.sdo in folder \"E:/altera/15.0/Project/FMETER/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1594625226038 ""} { "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4712 " "Peak virtual memory: 4712 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1594625226158 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Jul 13 15:27:06 2020 " "Processing ended: Mon Jul 13 15:27:06 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1594625226158 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1594625226158 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1594625226158 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1594625226158 ""} { "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 38 s " "Quartus II Full Compilation was successful. 0 errors, 38 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1594625226778 ""}