{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1594704679627 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 15.0.0 Build 145 04/22/2015 SJ Full Version " "Version 15.0.0 Build 145 04/22/2015 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1594704679637 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jul 14 13:31:19 2020 " "Processing started: Tue Jul 14 13:31:19 2020" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1594704679637 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1594704679637 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off mydds -c mydds " "Command: quartus_map --read_settings_files=on --write_settings_files=off mydds -c mydds" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1594704679637 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1594704680015 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "control.vhd 2 1 " "Found 2 design units, including 1 entities, in source file control.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 control-one " "Found design unit 1: control-one" {  } { { "control.vhd" "" { Text "E:/altera/15.0/Project/mydds/control.vhd" 14 -1 0 } }  } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1594704689656 ""} { "Info" "ISGN_ENTITY_NAME" "1 control " "Found entity 1: control" {  } { { "control.vhd" "" { Text "E:/altera/15.0/Project/mydds/control.vhd" 6 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1594704689656 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1594704689656 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "phase_acc.vhd 2 1 " "Found 2 design units, including 1 entities, in source file phase_acc.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 phase_acc-one " "Found design unit 1: phase_acc-one" {  } { { "phase_acc.vhd" "" { Text "E:/altera/15.0/Project/mydds/phase_acc.vhd" 14 -1 0 } }  } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1594704689659 ""} { "Info" "ISGN_ENTITY_NAME" "1 phase_acc " "Found entity 1: phase_acc" {  } { { "phase_acc.vhd" "" { Text "E:/altera/15.0/Project/mydds/phase_acc.vhd" 7 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1594704689659 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1594704689659 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom.vhd 2 1 " "Found 2 design units, including 1 entities, in source file rom.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rom-SYN " "Found design unit 1: rom-SYN" {  } { { "ROM.vhd" "" { Text "E:/altera/15.0/Project/mydds/ROM.vhd" 53 -1 0 } }  } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1594704689661 ""} { "Info" "ISGN_ENTITY_NAME" "1 ROM " "Found entity 1: ROM" {  } { { "ROM.vhd" "" { Text "E:/altera/15.0/Project/mydds/ROM.vhd" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1594704689661 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1594704689661 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mydds.bdf 1 1 " "Found 1 design units, including 1 entities, in source file mydds.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 mydds " "Found entity 1: mydds" {  } { { "mydds.bdf" "" { Schematic "E:/altera/15.0/Project/mydds/mydds.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1594704689662 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1594704689662 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "mydds " "Elaborating entity \"mydds\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1594704689725 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "control control:inst2 " "Elaborating entity \"control\" for hierarchy \"control:inst2\"" {  } { { "mydds.bdf" "inst2" { Schematic "E:/altera/15.0/Project/mydds/mydds.bdf" { { 120 376 552 232 "inst2" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689726 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ROM ROM:inst " "Elaborating entity \"ROM\" for hierarchy \"ROM:inst\"" {  } { { "mydds.bdf" "inst" { Schematic "E:/altera/15.0/Project/mydds/mydds.bdf" { { 96 920 1136 224 "inst" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689736 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ROM:inst\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"ROM:inst\|altsyncram:altsyncram_component\"" {  } { { "ROM.vhd" "altsyncram_component" { Text "E:/altera/15.0/Project/mydds/ROM.vhd" 60 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689779 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "ROM:inst\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"ROM:inst\|altsyncram:altsyncram_component\"" {  } { { "ROM.vhd" "" { Text "E:/altera/15.0/Project/mydds/ROM.vhd" 60 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1594704689806 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ROM:inst\|altsyncram:altsyncram_component " "Instantiated megafunction \"ROM:inst\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689816 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_b NONE " "Parameter \"address_aclr_b\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689816 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK1 " "Parameter \"address_reg_b\" = \"CLOCK1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689816 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "byte_size 8 " "Parameter \"byte_size\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689816 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "byteena_aclr_a UNUSED " "Parameter \"byteena_aclr_a\" = \"UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689816 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "byteena_aclr_b NONE " "Parameter \"byteena_aclr_b\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689816 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "byteena_reg_b CLOCK1 " "Parameter \"byteena_reg_b\" = \"CLOCK1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689816 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_core_a USE_INPUT_CLKEN " "Parameter \"clock_enable_core_a\" = \"USE_INPUT_CLKEN\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689816 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_core_b USE_INPUT_CLKEN " "Parameter \"clock_enable_core_b\" = \"USE_INPUT_CLKEN\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689816 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689816 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_b NORMAL " "Parameter \"clock_enable_input_b\" = \"NORMAL\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689816 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689816 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_b NORMAL " "Parameter \"clock_enable_output_b\" = \"NORMAL\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689816 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689816 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ecc_pipeline_stage_enabled FALSE " "Parameter \"ecc_pipeline_stage_enabled\" = \"FALSE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689816 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "enable_ecc FALSE " "Parameter \"enable_ecc\" = \"FALSE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689816 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "implement_in_les OFF " "Parameter \"implement_in_les\" = \"OFF\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689816 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_a UNUSED " "Parameter \"indata_aclr_a\" = \"UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689816 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_b NONE " "Parameter \"indata_aclr_b\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689816 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_reg_b CLOCK1 " "Parameter \"indata_reg_b\" = \"CLOCK1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689816 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file sindat.hex " "Parameter \"init_file\" = \"sindat.hex\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689816 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file_layout PORT_A " "Parameter \"init_file_layout\" = \"PORT_A\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689816 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689816 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 256 " "Parameter \"numwords_a\" = \"256\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689816 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 0 " "Parameter \"numwords_b\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689816 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Parameter \"operation_mode\" = \"ROM\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689816 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689816 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689816 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689816 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689816 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689816 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689816 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_aclr_b NONE " "Parameter \"rdcontrol_aclr_b\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689816 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK1 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689816 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689816 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_a NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_a\" = \"NEW_DATA_NO_NBE_READ\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689816 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_b NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_b\" = \"NEW_DATA_NO_NBE_READ\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689816 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "stratixiv_m144k_allow_dual_clocks ON " "Parameter \"stratixiv_m144k_allow_dual_clocks\" = \"ON\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689816 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689816 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 1 " "Parameter \"width_b\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689816 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689816 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_b 1 " "Parameter \"width_byteena_b\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689816 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_eccstatus 3 " "Parameter \"width_eccstatus\" = \"3\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689816 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 8 " "Parameter \"widthad_a\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689816 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 1 " "Parameter \"widthad_b\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689816 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_a UNUSED " "Parameter \"wrcontrol_aclr_a\" = \"UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689816 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_b NONE " "Parameter \"wrcontrol_aclr_b\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689816 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_wraddress_reg_b CLOCK1 " "Parameter \"wrcontrol_wraddress_reg_b\" = \"CLOCK1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689816 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689816 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689816 ""}  } { { "ROM.vhd" "" { Text "E:/altera/15.0/Project/mydds/ROM.vhd" 60 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1594704689816 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_v6r3.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_v6r3.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_v6r3 " "Found entity 1: altsyncram_v6r3" {  } { { "db/altsyncram_v6r3.tdf" "" { Text "E:/altera/15.0/Project/mydds/db/altsyncram_v6r3.tdf" 28 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1594704689864 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1594704689864 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_v6r3 ROM:inst\|altsyncram:altsyncram_component\|altsyncram_v6r3:auto_generated " "Elaborating entity \"altsyncram_v6r3\" for hierarchy \"ROM:inst\|altsyncram:altsyncram_component\|altsyncram_v6r3:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "e:/altera/15.0/quartus/libraries/megafunctions/altsyncram.tdf" 792 4 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689865 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "phase_acc phase_acc:inst3 " "Elaborating entity \"phase_acc\" for hierarchy \"phase_acc:inst3\"" {  } { { "mydds.bdf" "inst3" { Schematic "E:/altera/15.0/Project/mydds/mydds.bdf" { { 104 672 872 184 "inst3" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1594704689867 ""}
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "LEDB\[1\] VCC " "Pin \"LEDB\[1\]\" is stuck at VCC" {  } { { "mydds.bdf" "" { Schematic "E:/altera/15.0/Project/mydds/mydds.bdf" { { 256 592 768 272 "LEDB\[6..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1594704690575 "|mydds|LEDB[1]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1594704690575 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1594704690652 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1594704691386 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1594704691386 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "128 " "Implemented 128 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1594704691528 ""} { "Info" "ICUT_CUT_TM_OPINS" "23 " "Implemented 23 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1594704691528 ""} { "Info" "ICUT_CUT_TM_LCELLS" "95 " "Implemented 95 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1594704691528 ""} { "Info" "ICUT_CUT_TM_RAMS" "8 " "Implemented 8 RAM segments" {  } {  } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Quartus II" 0 -1 1594704691528 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1594704691528 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4858 " "Peak virtual memory: 4858 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1594704691610 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jul 14 13:31:31 2020 " "Processing ended: Tue Jul 14 13:31:31 2020" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1594704691610 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Elapsed time: 00:00:12" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1594704691610 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:23 " "Total CPU time (on all processors): 00:00:23" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1594704691610 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1594704691610 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1594704694036 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 15.0.0 Build 145 04/22/2015 SJ Full Version " "Version 15.0.0 Build 145 04/22/2015 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1594704694046 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jul 14 13:31:33 2020 " "Processing started: Tue Jul 14 13:31:33 2020" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1594704694046 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1594704694046 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off mydds -c mydds " "Command: quartus_fit --read_settings_files=off --write_settings_files=off mydds -c mydds" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1594704694046 ""}
{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1594704694175 ""}
{ "Info" "0" "" "Project  = mydds" {  } {  } 0 0 "Project  = mydds" 0 0 "Fitter" 0 0 1594704694175 ""}
{ "Info" "0" "" "Revision = mydds" {  } {  } 0 0 "Revision = mydds" 0 0 "Fitter" 0 0 1594704694175 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1594704694270 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "mydds EP4CE6E22C8 " "Selected device EP4CE6E22C8 for design \"mydds\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1594704694317 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1594704694382 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1594704694382 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1594704694511 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10E22C8 " "Device EP4CE10E22C8 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1594704694591 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15E22C8 " "Device EP4CE15E22C8 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1594704694591 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE22E22C8 " "Device EP4CE22E22C8 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1594704694591 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1594704694591 ""}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ 6 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location 6" {  } { { "e:/altera/15.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/altera/15.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "E:/altera/15.0/Project/mydds/" { { 0 { 0 ""} 0 362 9698 10655 0 0 ""}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1594704694596 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ 8 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location 8" {  } { { "e:/altera/15.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/altera/15.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "E:/altera/15.0/Project/mydds/" { { 0 { 0 ""} 0 364 9698 10655 0 0 ""}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1594704694596 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ 12 " "Pin ~ALTERA_DCLK~ is reserved at location 12" {  } { { "e:/altera/15.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/altera/15.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "E:/altera/15.0/Project/mydds/" { { 0 { 0 ""} 0 366 9698 10655 0 0 ""}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1594704694596 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ 13 " "Pin ~ALTERA_DATA0~ is reserved at location 13" {  } { { "e:/altera/15.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/altera/15.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "E:/altera/15.0/Project/mydds/" { { 0 { 0 ""} 0 368 9698 10655 0 0 ""}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1594704694596 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ 101 " "Pin ~ALTERA_nCEO~ is reserved at location 101" {  } { { "e:/altera/15.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/altera/15.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "E:/altera/15.0/Project/mydds/" { { 0 { 0 ""} 0 370 9698 10655 0 0 ""}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1594704694596 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1594704694596 ""}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1594704694598 ""}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1594704694600 ""}
{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "8 25 " "No exact pin location assignment(s) for 8 pins of 25 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." {  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1594704694862 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "mydds.sdc " "Synopsys Design Constraints File file not found: 'mydds.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1594704695071 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1594704695072 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1594704695076 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1594704695076 ""}
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1594704695077 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLK0~input (placed in PIN 24 (CLK2, DIFFCLK_1p)) " "Automatically promoted node CLK0~input (placed in PIN 24 (CLK2, DIFFCLK_1p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G4 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1594704695092 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "L~output " "Destination node L~output" {  } { { "mydds.bdf" "" { Schematic "E:/altera/15.0/Project/mydds/mydds.bdf" { { 368 1032 1208 384 "L" "" } } } } { "temporary_test_loc" "" { Generic "E:/altera/15.0/Project/mydds/" { { 0 { 0 ""} 0 333 9698 10655 0 0 ""}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1594704695092 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1594704695092 ""}  } { { "mydds.bdf" "" { Schematic "E:/altera/15.0/Project/mydds/mydds.bdf" { { 368 528 696 384 "CLK0" "" } } } } { "temporary_test_loc" "" { Generic "E:/altera/15.0/Project/mydds/" { { 0 { 0 ""} 0 356 9698 10655 0 0 ""}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1594704695092 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "inst4  " "Automatically promoted node inst4 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1594704695093 ""}  } { { "mydds.bdf" "" { Schematic "E:/altera/15.0/Project/mydds/mydds.bdf" { { 128 224 288 208 "inst4" "" } } } } { "temporary_test_loc" "" { Generic "E:/altera/15.0/Project/mydds/" { { 0 { 0 ""} 0 108 9698 10655 0 0 ""}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1594704695093 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1594704695415 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1594704695416 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1594704695416 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1594704695417 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1594704695417 ""}
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1594704695418 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1594704695418 ""}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1594704695419 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1594704695419 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1594704695420 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1594704695420 ""}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "8 unused 2.5V 0 8 0 " "Number of I/O pins in group: 8 (unused VREF, 2.5V VCCIO, 0 input, 8 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." {  } {  } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1594704695424 ""}  } {  } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1594704695424 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1594704695424 ""}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 4 7 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used --  7 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1594704695426 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 1 7 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  7 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1594704695426 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 11 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  11 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1594704695426 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 14 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  14 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1594704695426 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use 2.5V 1 12 " "I/O bank number 5 does not use VREF pins and has 2.5V VCCIO pins. 1 total pin(s) used --  12 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1594704695426 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 2 8 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used --  8 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1594704695426 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use 2.5V 10 3 " "I/O bank number 7 does not use VREF pins and has 2.5V VCCIO pins. 10 total pin(s) used --  3 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1594704695426 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use 2.5V 4 8 " "I/O bank number 8 does not use VREF pins and has 2.5V VCCIO pins. 4 total pin(s) used --  8 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1594704695426 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1594704695426 ""}  } {  } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1594704695426 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1594704695440 ""}
{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." {  } {  } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1594704695450 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1594704696055 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1594704696103 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1594704696117 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1594704696946 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1594704696947 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1594704697260 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X23_Y12 X34_Y24 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y12 to location X34_Y24" {  } { { "loc" "" { Generic "E:/altera/15.0/Project/mydds/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y12 to location X34_Y24"} { { 12 { 0 ""} 23 12 12 13 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1594704697660 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1594704697659 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1594704697928 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1594704697929 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1594704697929 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.26 " "Total time spent on timing analysis during the Fitter is 0.26 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1594704697940 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1594704698012 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1594704698175 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1594704698239 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1594704698409 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1594704698778 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/altera/15.0/Project/mydds/output_files/mydds.fit.smsg " "Generated suppressed messages file E:/altera/15.0/Project/mydds/output_files/mydds.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1594704699109 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5618 " "Peak virtual memory: 5618 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1594704699650 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jul 14 13:31:39 2020 " "Processing ended: Tue Jul 14 13:31:39 2020" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1594704699650 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1594704699650 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1594704699650 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1594704699650 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1594704701856 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 15.0.0 Build 145 04/22/2015 SJ Full Version " "Version 15.0.0 Build 145 04/22/2015 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1594704701867 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jul 14 13:31:41 2020 " "Processing started: Tue Jul 14 13:31:41 2020" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1594704701867 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1594704701867 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off mydds -c mydds " "Command: quartus_asm --read_settings_files=off --write_settings_files=off mydds -c mydds" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1594704701867 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1594704702608 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1594704702641 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4740 " "Peak virtual memory: 4740 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1594704702931 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jul 14 13:31:42 2020 " "Processing ended: Tue Jul 14 13:31:42 2020" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1594704702931 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1594704702931 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1594704702931 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1594704702931 ""}
{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1594704703562 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1594704705450 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 15.0.0 Build 145 04/22/2015 SJ Full Version " "Version 15.0.0 Build 145 04/22/2015 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1594704705463 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jul 14 13:31:45 2020 " "Processing started: Tue Jul 14 13:31:45 2020" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1594704705463 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1594704705463 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta mydds -c mydds " "Command: quartus_sta mydds -c mydds" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1594704705464 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #11" {  } {  } 0 0 "qsta_default_script.tcl version: #11" 0 0 "Quartus II" 0 0 1594704705614 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1594704705740 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1594704705798 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1594704705798 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "mydds.sdc " "Synopsys Design Constraints File file not found: 'mydds.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1594704706140 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1594704706140 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLK0 CLK0 " "create_clock -period 1.000 -name CLK0 CLK0" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1594704706142 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst4 inst4 " "create_clock -period 1.000 -name inst4 inst4" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1594704706142 ""}  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1594704706142 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1594704706194 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1594704706195 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1594704706196 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1594704706215 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1594704706247 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1594704706247 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -4.571 " "Worst-case setup slack is -4.571" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1594704706257 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1594704706257 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -4.571            -138.554 CLK0  " "   -4.571            -138.554 CLK0 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1594704706257 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.281              -5.772 inst4  " "   -1.281              -5.772 inst4 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1594704706257 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1594704706257 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.453 " "Worst-case hold slack is 0.453" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1594704706271 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1594704706271 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.453               0.000 inst4  " "    0.453               0.000 inst4 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1594704706271 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.606               0.000 CLK0  " "    0.606               0.000 CLK0 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1594704706271 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1594704706271 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1594704706280 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1594704706290 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.201 " "Worst-case minimum pulse width slack is -3.201" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1594704706299 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1594704706299 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.201             -80.880 CLK0  " "   -3.201             -80.880 CLK0 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1594704706299 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.487              -7.435 inst4  " "   -1.487              -7.435 inst4 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1594704706299 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1594704706299 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1594704706428 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1594704706451 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1594704706682 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1594704706763 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1594704706778 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1594704706778 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -4.006 " "Worst-case setup slack is -4.006" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1594704706789 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1594704706789 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -4.006            -122.251 CLK0  " "   -4.006            -122.251 CLK0 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1594704706789 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.034              -4.701 inst4  " "   -1.034              -4.701 inst4 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1594704706789 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1594704706789 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.404 " "Worst-case hold slack is 0.404" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1594704706816 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1594704706816 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.404               0.000 inst4  " "    0.404               0.000 inst4 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1594704706816 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.538               0.000 CLK0  " "    0.538               0.000 CLK0 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1594704706816 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1594704706816 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1594704706829 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1594704706841 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.201 " "Worst-case minimum pulse width slack is -3.201" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1594704706851 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1594704706851 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.201             -80.880 CLK0  " "   -3.201             -80.880 CLK0 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1594704706851 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.487              -7.435 inst4  " "   -1.487              -7.435 inst4 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1594704706851 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1594704706851 ""}
{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1594704706989 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1594704707236 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1594704707240 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1594704707240 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.769 " "Worst-case setup slack is -1.769" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1594704707253 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1594704707253 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.769             -45.630 CLK0  " "   -1.769             -45.630 CLK0 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1594704707253 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.004               0.000 inst4  " "    0.004               0.000 inst4 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1594704707253 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1594704707253 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.185 " "Worst-case hold slack is 0.185" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1594704707268 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1594704707268 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.185               0.000 inst4  " "    0.185               0.000 inst4 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1594704707268 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.254               0.000 CLK0  " "    0.254               0.000 CLK0 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1594704707268 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1594704707268 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1594704707289 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1594704707320 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1594704707336 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1594704707336 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000             -48.503 CLK0  " "   -3.000             -48.503 CLK0 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1594704707336 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -5.000 inst4  " "   -1.000              -5.000 inst4 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1594704707336 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1594704707336 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1594704708056 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1594704708056 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4850 " "Peak virtual memory: 4850 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1594704708224 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jul 14 13:31:48 2020 " "Processing ended: Tue Jul 14 13:31:48 2020" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1594704708224 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1594704708224 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1594704708224 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1594704708224 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1594704710458 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 64-Bit " "Running Quartus II 64-Bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 15.0.0 Build 145 04/22/2015 SJ Full Version " "Version 15.0.0 Build 145 04/22/2015 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1594704710467 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jul 14 13:31:50 2020 " "Processing started: Tue Jul 14 13:31:50 2020" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1594704710467 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1594704710467 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off mydds -c mydds " "Command: quartus_eda --read_settings_files=off --write_settings_files=off mydds -c mydds" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1594704710467 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "mydds_8_1200mv_85c_slow.vho E:/altera/15.0/Project/mydds/simulation/modelsim/ simulation " "Generated file mydds_8_1200mv_85c_slow.vho in folder \"E:/altera/15.0/Project/mydds/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1594704711043 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "mydds_8_1200mv_0c_slow.vho E:/altera/15.0/Project/mydds/simulation/modelsim/ simulation " "Generated file mydds_8_1200mv_0c_slow.vho in folder \"E:/altera/15.0/Project/mydds/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1594704711094 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "mydds_min_1200mv_0c_fast.vho E:/altera/15.0/Project/mydds/simulation/modelsim/ simulation " "Generated file mydds_min_1200mv_0c_fast.vho in folder \"E:/altera/15.0/Project/mydds/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1594704711145 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "mydds.vho E:/altera/15.0/Project/mydds/simulation/modelsim/ simulation " "Generated file mydds.vho in folder \"E:/altera/15.0/Project/mydds/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1594704711195 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "mydds_8_1200mv_85c_vhd_slow.sdo E:/altera/15.0/Project/mydds/simulation/modelsim/ simulation " "Generated file mydds_8_1200mv_85c_vhd_slow.sdo in folder \"E:/altera/15.0/Project/mydds/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1594704711250 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "mydds_8_1200mv_0c_vhd_slow.sdo E:/altera/15.0/Project/mydds/simulation/modelsim/ simulation " "Generated file mydds_8_1200mv_0c_vhd_slow.sdo in folder \"E:/altera/15.0/Project/mydds/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1594704711304 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "mydds_min_1200mv_0c_vhd_fast.sdo E:/altera/15.0/Project/mydds/simulation/modelsim/ simulation " "Generated file mydds_min_1200mv_0c_vhd_fast.sdo in folder \"E:/altera/15.0/Project/mydds/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1594704711358 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "mydds_vhd.sdo E:/altera/15.0/Project/mydds/simulation/modelsim/ simulation " "Generated file mydds_vhd.sdo in folder \"E:/altera/15.0/Project/mydds/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1594704711408 ""}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4718 " "Peak virtual memory: 4718 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1594704711521 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jul 14 13:31:51 2020 " "Processing ended: Tue Jul 14 13:31:51 2020" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1594704711521 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1594704711521 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1594704711521 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1594704711521 ""}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 9 s " "Quartus II Full Compilation was successful. 0 errors, 9 warnings" {  } {  } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1594704712174 ""}