{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1632973520810 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.0 Build 156 04/24/2013 SJ Full Version " "Version 13.0.0 Build 156 04/24/2013 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1632973520810 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 30 11:45:20 2021 " "Processing started: Thu Sep 30 11:45:20 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1632973520810 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1632973520810 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off HDB3 -c HDB3 " "Command: quartus_map --read_settings_files=on --write_settings_files=off HDB3 -c HDB3" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1632973520810 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1632973521248 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "add_v.v 1 1 " "Found 1 design units, including 1 entities, in source file add_v.v" { { "Info" "ISGN_ENTITY_NAME" "1 add_v " "Found entity 1: add_v" {  } { { "add_v.v" "" { Text "E:/altera/13.0/projects/HDB3_FPGA/add_v.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1632973521303 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1632973521303 ""}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "add_b.v(26) " "Verilog HDL information at add_b.v(26): always construct contains both blocking and non-blocking assignments" {  } { { "add_b.v" "" { Text "E:/altera/13.0/projects/HDB3_FPGA/add_b.v" 26 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1632973521306 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "add_b.v 1 1 " "Found 1 design units, including 1 entities, in source file add_b.v" { { "Info" "ISGN_ENTITY_NAME" "1 add_b " "Found entity 1: add_b" {  } { { "add_b.v" "" { Text "E:/altera/13.0/projects/HDB3_FPGA/add_b.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1632973521307 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1632973521307 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "polar.v 1 1 " "Found 1 design units, including 1 entities, in source file polar.v" { { "Info" "ISGN_ENTITY_NAME" "1 polar " "Found entity 1: polar" {  } { { "polar.v" "" { Text "E:/altera/13.0/projects/HDB3_FPGA/polar.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1632973521309 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1632973521309 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "change.v 1 1 " "Found 1 design units, including 1 entities, in source file change.v" { { "Info" "ISGN_ENTITY_NAME" "1 change " "Found entity 1: change" {  } { { "change.v" "" { Text "E:/altera/13.0/projects/HDB3_FPGA/change.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1632973521312 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1632973521312 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "hdb3.v 1 1 " "Found 1 design units, including 1 entities, in source file hdb3.v" { { "Info" "ISGN_ENTITY_NAME" "1 HDB3 " "Found entity 1: HDB3" {  } { { "HDB3.v" "" { Text "E:/altera/13.0/projects/HDB3_FPGA/HDB3.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1632973521314 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1632973521314 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "m_sequence.v 1 1 " "Found 1 design units, including 1 entities, in source file m_sequence.v" { { "Info" "ISGN_ENTITY_NAME" "1 m_sequence " "Found entity 1: m_sequence" {  } { { "m_sequence.v" "" { Text "E:/altera/13.0/projects/HDB3_FPGA/m_sequence.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1632973521317 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1632973521317 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "even256_div.v 1 1 " "Found 1 design units, including 1 entities, in source file even256_div.v" { { "Info" "ISGN_ENTITY_NAME" "1 even256_div " "Found entity 1: even256_div" {  } { { "even256_div.v" "" { Text "E:/altera/13.0/projects/HDB3_FPGA/even256_div.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1632973521321 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1632973521321 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "delvb.v 1 1 " "Found 1 design units, including 1 entities, in source file delvb.v" { { "Info" "ISGN_ENTITY_NAME" "1 delvb " "Found entity 1: delvb" {  } { { "delvb.v" "" { Text "E:/altera/13.0/projects/HDB3_FPGA/delvb.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1632973521324 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1632973521324 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "trans8to1.v 1 1 " "Found 1 design units, including 1 entities, in source file trans8to1.v" { { "Info" "ISGN_ENTITY_NAME" "1 trans8to1 " "Found entity 1: trans8to1" {  } { { "trans8to1.v" "" { Text "E:/altera/13.0/projects/HDB3_FPGA/trans8to1.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1632973521327 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1632973521327 ""}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "findv.v(14) " "Verilog HDL information at findv.v(14): always construct contains both blocking and non-blocking assignments" {  } { { "findv.v" "" { Text "E:/altera/13.0/projects/HDB3_FPGA/findv.v" 14 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1632973521330 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "findv.v 1 1 " "Found 1 design units, including 1 entities, in source file findv.v" { { "Info" "ISGN_ENTITY_NAME" "1 findv " "Found entity 1: findv" {  } { { "findv.v" "" { Text "E:/altera/13.0/projects/HDB3_FPGA/findv.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1632973521330 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1632973521330 ""}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "recover.v(17) " "Verilog HDL information at recover.v(17): always construct contains both blocking and non-blocking assignments" {  } { { "recover.v" "" { Text "E:/altera/13.0/projects/HDB3_FPGA/recover.v" 17 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1632973521333 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "recover.v 1 1 " "Found 1 design units, including 1 entities, in source file recover.v" { { "Info" "ISGN_ENTITY_NAME" "1 recover " "Found entity 1: recover" {  } { { "recover.v" "" { Text "E:/altera/13.0/projects/HDB3_FPGA/recover.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1632973521333 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1632973521333 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "load HDB3.v(24) " "Verilog HDL Implicit Net warning at HDB3.v(24): created implicit net for \"load\"" {  } { { "HDB3.v" "" { Text "E:/altera/13.0/projects/HDB3_FPGA/HDB3.v" 24 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1632973521333 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "HDB3 " "Elaborating entity \"HDB3\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1632973521379 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "even256_div even256_div:div256 " "Elaborating entity \"even256_div\" for hierarchy \"even256_div:div256\"" {  } { { "HDB3.v" "div256" { Text "E:/altera/13.0/projects/HDB3_FPGA/HDB3.v" 21 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1632973521396 ""}
{ "Warning" "WSGN_SEARCH_FILE" "even16_div.v 1 1 " "Using design file even16_div.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 even16_div " "Found entity 1: even16_div" {  } { { "even16_div.v" "" { Text "E:/altera/13.0/projects/HDB3_FPGA/even16_div.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1632973521421 ""}  } {  } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Quartus II" 0 -1 1632973521421 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "even16_div even16_div:div16 " "Elaborating entity \"even16_div\" for hierarchy \"even16_div:div16\"" {  } { { "HDB3.v" "div16" { Text "E:/altera/13.0/projects/HDB3_FPGA/HDB3.v" 22 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1632973521423 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "m_sequence m_sequence:m " "Elaborating entity \"m_sequence\" for hierarchy \"m_sequence:m\"" {  } { { "HDB3.v" "m" { Text "E:/altera/13.0/projects/HDB3_FPGA/HDB3.v" 24 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1632973521427 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_v add_v:u1 " "Elaborating entity \"add_v\" for hierarchy \"add_v:u1\"" {  } { { "HDB3.v" "u1" { Text "E:/altera/13.0/projects/HDB3_FPGA/HDB3.v" 26 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1632973521430 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 add_v.v(18) " "Verilog HDL assignment warning at add_v.v(18): truncated value with size 32 to match size of target (2)" {  } { { "add_v.v" "" { Text "E:/altera/13.0/projects/HDB3_FPGA/add_v.v" 18 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1632973521431 "|HDB3|add_v:u1"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_b add_b:u2 " "Elaborating entity \"add_b\" for hierarchy \"add_b:u2\"" {  } { { "HDB3.v" "u2" { Text "E:/altera/13.0/projects/HDB3_FPGA/HDB3.v" 27 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1632973521433 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "polar polar:u3 " "Elaborating entity \"polar\" for hierarchy \"polar:u3\"" {  } { { "HDB3.v" "u3" { Text "E:/altera/13.0/projects/HDB3_FPGA/HDB3.v" 28 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1632973521436 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "change change:u4 " "Elaborating entity \"change\" for hierarchy \"change:u4\"" {  } { { "HDB3.v" "u4" { Text "E:/altera/13.0/projects/HDB3_FPGA/HDB3.v" 29 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1632973521439 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "recover recover:u8 " "Elaborating entity \"recover\" for hierarchy \"recover:u8\"" {  } { { "HDB3.v" "u8" { Text "E:/altera/13.0/projects/HDB3_FPGA/HDB3.v" 31 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1632973521444 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 recover.v(40) " "Verilog HDL assignment warning at recover.v(40): truncated value with size 32 to match size of target (4)" {  } { { "recover.v" "" { Text "E:/altera/13.0/projects/HDB3_FPGA/recover.v" 40 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1632973521445 "|HDB3|recover:u8"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "trans8to1 trans8to1:u5 " "Elaborating entity \"trans8to1\" for hierarchy \"trans8to1:u5\"" {  } { { "HDB3.v" "u5" { Text "E:/altera/13.0/projects/HDB3_FPGA/HDB3.v" 33 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1632973521447 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "findv findv:u6 " "Elaborating entity \"findv\" for hierarchy \"findv:u6\"" {  } { { "HDB3.v" "u6" { Text "E:/altera/13.0/projects/HDB3_FPGA/HDB3.v" 34 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1632973521450 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "delvb delvb:u7 " "Elaborating entity \"delvb\" for hierarchy \"delvb:u7\"" {  } { { "HDB3.v" "u7" { Text "E:/altera/13.0/projects/HDB3_FPGA/HDB3.v" 35 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1632973521453 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 delvb.v(49) " "Verilog HDL assignment warning at delvb.v(49): truncated value with size 32 to match size of target (1)" {  } { { "delvb.v" "" { Text "E:/altera/13.0/projects/HDB3_FPGA/delvb.v" 49 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1632973521454 "|HDB3|delvb:u7"}
{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" {  } { { "change.v" "" { Text "E:/altera/13.0/projects/HDB3_FPGA/change.v" 11 -1 0 } } { "recover.v" "" { Text "E:/altera/13.0/projects/HDB3_FPGA/recover.v" 30 -1 0 } } { "m_sequence.v" "" { Text "E:/altera/13.0/projects/HDB3_FPGA/m_sequence.v" 18 -1 0 } } { "polar.v" "" { Text "E:/altera/13.0/projects/HDB3_FPGA/polar.v" 8 -1 0 } }  } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1632973521834 ""}
{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Quartus II" 0 -1 1632973521834 ""}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "4 " "4 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1632973522192 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/altera/13.0/projects/HDB3_FPGA/output_files/HDB3.map.smsg " "Generated suppressed messages file E:/altera/13.0/projects/HDB3_FPGA/output_files/HDB3.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1632973522266 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1632973522453 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1632973522453 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "133 " "Implemented 133 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "11 " "Implemented 11 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1632973522499 ""} { "Info" "ICUT_CUT_TM_OPINS" "33 " "Implemented 33 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1632973522499 ""} { "Info" "ICUT_CUT_TM_LCELLS" "89 " "Implemented 89 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1632973522499 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1632973522499 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4600 " "Peak virtual memory: 4600 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1632973522534 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 30 11:45:22 2021 " "Processing ended: Thu Sep 30 11:45:22 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1632973522534 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1632973522534 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1632973522534 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1632973522534 ""}