{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1631690602099 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.0 Build 156 04/24/2013 SJ Full Version " "Version 13.0.0 Build 156 04/24/2013 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1631690602099 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 15 15:23:21 2021 " "Processing started: Wed Sep 15 15:23:21 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1631690602099 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1631690602099 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off HDB3 -c HDB3 " "Command: quartus_map --read_settings_files=on --write_settings_files=off HDB3 -c HDB3" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1631690602099 ""} { "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." { } { } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1631690602374 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "add_v.v 1 1 " "Found 1 design units, including 1 entities, in source file add_v.v" { { "Info" "ISGN_ENTITY_NAME" "1 add_v " "Found entity 1: add_v" { } { { "add_v.v" "" { Text "E:/altera/13.0/PRJECT/HDB3/add_v.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1631690602409 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1631690602409 ""} { "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "add_b.v(27) " "Verilog HDL information at add_b.v(27): always construct contains both blocking and non-blocking assignments" { } { { "add_b.v" "" { Text "E:/altera/13.0/PRJECT/HDB3/add_b.v" 27 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1631690602409 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "add_b.v 1 1 " "Found 1 design units, including 1 entities, in source file add_b.v" { { "Info" "ISGN_ENTITY_NAME" "1 add_b " "Found entity 1: add_b" { } { { "add_b.v" "" { Text "E:/altera/13.0/PRJECT/HDB3/add_b.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1631690602409 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1631690602409 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "polar.v 1 1 " "Found 1 design units, including 1 entities, in source file polar.v" { { "Info" "ISGN_ENTITY_NAME" "1 polar " "Found entity 1: polar" { } { { "polar.v" "" { Text "E:/altera/13.0/PRJECT/HDB3/polar.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1631690602414 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1631690602414 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "change.v 1 1 " "Found 1 design units, including 1 entities, in source file change.v" { { "Info" "ISGN_ENTITY_NAME" "1 change " "Found entity 1: change" { } { { "change.v" "" { Text "E:/altera/13.0/PRJECT/HDB3/change.v" 2 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1631690602414 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1631690602414 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "hdb3.v 1 1 " "Found 1 design units, including 1 entities, in source file hdb3.v" { { "Info" "ISGN_ENTITY_NAME" "1 HDB3 " "Found entity 1: HDB3" { } { { "HDB3.v" "" { Text "E:/altera/13.0/PRJECT/HDB3/HDB3.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1631690602418 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1631690602418 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "m_sequence.v 1 1 " "Found 1 design units, including 1 entities, in source file m_sequence.v" { { "Info" "ISGN_ENTITY_NAME" "1 m_sequence " "Found entity 1: m_sequence" { } { { "m_sequence.v" "" { Text "E:/altera/13.0/PRJECT/HDB3/m_sequence.v" 2 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1631690602418 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1631690602418 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "even_div16.v 1 1 " "Found 1 design units, including 1 entities, in source file even_div16.v" { { "Info" "ISGN_ENTITY_NAME" "1 even_div16 " "Found entity 1: even_div16" { } { { "even_div16.v" "" { Text "E:/altera/13.0/PRJECT/HDB3/even_div16.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1631690602418 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1631690602418 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "even256_div.v 1 1 " "Found 1 design units, including 1 entities, in source file even256_div.v" { { "Info" "ISGN_ENTITY_NAME" "1 even256_div " "Found entity 1: even256_div" { } { { "even256_div.v" "" { Text "E:/altera/13.0/PRJECT/HDB3/even256_div.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1631690602418 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1631690602418 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "delvb.v 1 1 " "Found 1 design units, including 1 entities, in source file delvb.v" { { "Info" "ISGN_ENTITY_NAME" "1 delvb " "Found entity 1: delvb" { } { { "delvb.v" "" { Text "E:/altera/13.0/PRJECT/HDB3/delvb.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1631690602424 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1631690602424 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "trans8to1.v 1 1 " "Found 1 design units, including 1 entities, in source file trans8to1.v" { { "Info" "ISGN_ENTITY_NAME" "1 trans8to1 " "Found entity 1: trans8to1" { } { { "trans8to1.v" "" { Text "E:/altera/13.0/PRJECT/HDB3/trans8to1.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1631690602424 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1631690602424 ""} { "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "findv.v(14) " "Verilog HDL information at findv.v(14): always construct contains both blocking and non-blocking assignments" { } { { "findv.v" "" { Text "E:/altera/13.0/PRJECT/HDB3/findv.v" 14 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1631690602424 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "findv.v 1 1 " "Found 1 design units, including 1 entities, in source file findv.v" { { "Info" "ISGN_ENTITY_NAME" "1 findv " "Found entity 1: findv" { } { { "findv.v" "" { Text "E:/altera/13.0/PRJECT/HDB3/findv.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1631690602424 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1631690602424 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "decode.v 1 1 " "Found 1 design units, including 1 entities, in source file decode.v" { { "Info" "ISGN_ENTITY_NAME" "1 decode " "Found entity 1: decode" { } { { "decode.v" "" { Text "E:/altera/13.0/PRJECT/HDB3/decode.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1631690602429 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1631690602429 ""} { "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "recover.v(16) " "Verilog HDL information at recover.v(16): always construct contains both blocking and non-blocking assignments" { } { { "recover.v" "" { Text "E:/altera/13.0/PRJECT/HDB3/recover.v" 16 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1631690602429 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "recover.v 1 1 " "Found 1 design units, including 1 entities, in source file recover.v" { { "Info" "ISGN_ENTITY_NAME" "1 recover " "Found entity 1: recover" { } { { "recover.v" "" { Text "E:/altera/13.0/PRJECT/HDB3/recover.v" 2 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1631690602429 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1631690602429 ""} { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "load HDB3.v(24) " "Verilog HDL Implicit Net warning at HDB3.v(24): created implicit net for \"load\"" { } { { "HDB3.v" "" { Text "E:/altera/13.0/PRJECT/HDB3/HDB3.v" 24 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1631690602429 ""} { "Info" "ISGN_START_ELABORATION_TOP" "HDB3 " "Elaborating entity \"HDB3\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1631690602454 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "even256_div even256_div:div256 " "Elaborating entity \"even256_div\" for hierarchy \"even256_div:div256\"" { } { { "HDB3.v" "div256" { Text "E:/altera/13.0/PRJECT/HDB3/HDB3.v" 21 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1631690602464 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "even_div16 even_div16:div16 " "Elaborating entity \"even_div16\" for hierarchy \"even_div16:div16\"" { } { { "HDB3.v" "div16" { Text "E:/altera/13.0/PRJECT/HDB3/HDB3.v" 22 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1631690602464 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "m_sequence m_sequence:m " "Elaborating entity \"m_sequence\" for hierarchy \"m_sequence:m\"" { } { { "HDB3.v" "m" { Text "E:/altera/13.0/PRJECT/HDB3/HDB3.v" 24 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1631690602464 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_v add_v:u1 " "Elaborating entity \"add_v\" for hierarchy \"add_v:u1\"" { } { { "HDB3.v" "u1" { Text "E:/altera/13.0/PRJECT/HDB3/HDB3.v" 26 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1631690602464 ""} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 add_v.v(18) " "Verilog HDL assignment warning at add_v.v(18): truncated value with size 32 to match size of target (2)" { } { { "add_v.v" "" { Text "E:/altera/13.0/PRJECT/HDB3/add_v.v" 18 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1631690602464 "|HDB3|add_v:u1"} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_b add_b:u2 " "Elaborating entity \"add_b\" for hierarchy \"add_b:u2\"" { } { { "HDB3.v" "u2" { Text "E:/altera/13.0/PRJECT/HDB3/HDB3.v" 27 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1631690602474 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "polar polar:u3 " "Elaborating entity \"polar\" for hierarchy \"polar:u3\"" { } { { "HDB3.v" "u3" { Text "E:/altera/13.0/PRJECT/HDB3/HDB3.v" 28 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1631690602474 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "change change:u4 " "Elaborating entity \"change\" for hierarchy \"change:u4\"" { } { { "HDB3.v" "u4" { Text "E:/altera/13.0/PRJECT/HDB3/HDB3.v" 29 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1631690602474 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "recover recover:u8 " "Elaborating entity \"recover\" for hierarchy \"recover:u8\"" { } { { "HDB3.v" "u8" { Text "E:/altera/13.0/PRJECT/HDB3/HDB3.v" 31 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1631690602479 ""} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 recover.v(34) " "Verilog HDL assignment warning at recover.v(34): truncated value with size 32 to match size of target (4)" { } { { "recover.v" "" { Text "E:/altera/13.0/PRJECT/HDB3/recover.v" 34 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1631690602479 "|HDB3|recover:u8"} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "trans8to1 trans8to1:u5 " "Elaborating entity \"trans8to1\" for hierarchy \"trans8to1:u5\"" { } { { "HDB3.v" "u5" { Text "E:/altera/13.0/PRJECT/HDB3/HDB3.v" 33 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1631690602479 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "findv findv:u6 " "Elaborating entity \"findv\" for hierarchy \"findv:u6\"" { } { { "HDB3.v" "u6" { Text "E:/altera/13.0/PRJECT/HDB3/HDB3.v" 34 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1631690602479 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "delvb delvb:u7 " "Elaborating entity \"delvb\" for hierarchy \"delvb:u7\"" { } { { "HDB3.v" "u7" { Text "E:/altera/13.0/PRJECT/HDB3/HDB3.v" 35 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1631690602484 ""} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 delvb.v(45) " "Verilog HDL assignment warning at delvb.v(45): truncated value with size 32 to match size of target (1)" { } { { "delvb.v" "" { Text "E:/altera/13.0/PRJECT/HDB3/delvb.v" 45 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1631690602484 "|HDB3|delvb:u7"} { "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "change.v" "" { Text "E:/altera/13.0/PRJECT/HDB3/change.v" 13 -1 0 } } { "recover.v" "" { Text "E:/altera/13.0/PRJECT/HDB3/recover.v" 26 -1 0 } } { "m_sequence.v" "" { Text "E:/altera/13.0/PRJECT/HDB3/m_sequence.v" 22 -1 0 } } { "polar.v" "" { Text "E:/altera/13.0/PRJECT/HDB3/polar.v" 7 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1631690602794 ""} { "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Quartus II" 0 -1 1631690602794 ""} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "4 " "4 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1631690602944 ""} { "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/altera/13.0/PRJECT/HDB3/output_files/HDB3.map.smsg " "Generated suppressed messages file E:/altera/13.0/PRJECT/HDB3/output_files/HDB3.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1631690602979 ""} { "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1631690603054 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1631690603054 ""} { "Info" "ICUT_CUT_TM_SUMMARY" "133 " "Implemented 133 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "11 " "Implemented 11 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1631690603084 ""} { "Info" "ICUT_CUT_TM_OPINS" "33 " "Implemented 33 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1631690603084 ""} { "Info" "ICUT_CUT_TM_LCELLS" "89 " "Implemented 89 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1631690603084 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1631690603084 ""} { "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4589 " "Peak virtual memory: 4589 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1631690603104 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 15 15:23:23 2021 " "Processing ended: Wed Sep 15 15:23:23 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1631690603104 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1631690603104 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1631690603104 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1631690603104 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1631690604156 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.0 Build 156 04/24/2013 SJ Full Version " "Version 13.0.0 Build 156 04/24/2013 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1631690604156 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 15 15:23:23 2021 " "Processing started: Wed Sep 15 15:23:23 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1631690604156 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1631690604156 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off HDB3 -c HDB3 " "Command: quartus_fit --read_settings_files=off --write_settings_files=off HDB3 -c HDB3" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1631690604156 ""} { "Info" "0" "" "qfit2_default_script.tcl version: #3" { } { } 0 0 "qfit2_default_script.tcl version: #3" 0 0 "Fitter" 0 0 1631690604216 ""} { "Info" "0" "" "Project = HDB3" { } { } 0 0 "Project = HDB3" 0 0 "Fitter" 0 0 1631690604216 ""} { "Info" "0" "" "Revision = HDB3" { } { } 0 0 "Revision = HDB3" 0 0 "Fitter" 0 0 1631690604216 ""} { "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." { } { } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Fitter" 0 -1 1631690604291 ""} { "Info" "IMPP_MPP_USER_DEVICE" "HDB3 EP2C8T144C8 " "Selected device EP2C8T144C8 for design \"HDB3\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1631690604301 ""} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1631690604321 ""} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1631690604321 ""} { "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1631690604361 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5T144C8 " "Device EP2C5T144C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1631690604570 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5T144I8 " "Device EP2C5T144I8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1631690604570 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8T144I8 " "Device EP2C8T144I8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1631690604570 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1631690604570 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Pin ~ASDO~ is reserved at location 1" { } { { "e:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/altera/13.0/quartus/bin64/pin_planner.ppl" { ~ASDO~ } } } { "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/altera/13.0/PRJECT/HDB3/" { { 0 { 0 ""} 0 236 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1631690604570 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Pin ~nCSO~ is reserved at location 2" { } { { "e:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/altera/13.0/quartus/bin64/pin_planner.ppl" { ~nCSO~ } } } { "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/altera/13.0/PRJECT/HDB3/" { { 0 { 0 ""} 0 237 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1631690604570 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS54p/nCEO~ 76 " "Pin ~LVDS54p/nCEO~ is reserved at location 76" { } { { "e:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/altera/13.0/quartus/bin64/pin_planner.ppl" { ~LVDS54p/nCEO~ } } } { "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~LVDS54p/nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/altera/13.0/PRJECT/HDB3/" { { 0 { 0 ""} 0 238 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1631690604570 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1631690604570 ""} { "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "11 44 " "No exact pin location assignment(s) for 11 pins of 44 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "clk_256_da " "Pin clk_256_da not assigned to an exact location on the device" { } { { "e:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/altera/13.0/quartus/bin64/pin_planner.ppl" { clk_256_da } } } { "HDB3.v" "" { Text "E:/altera/13.0/PRJECT/HDB3/HDB3.v" 11 0 0 } } { "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk_256_da } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/altera/13.0/PRJECT/HDB3/" { { 0 { 0 ""} 0 56 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1631690604590 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "outv\[0\] " "Pin outv\[0\] not assigned to an exact location on the device" { } { { "e:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/altera/13.0/quartus/bin64/pin_planner.ppl" { outv[0] } } } { "HDB3.v" "" { Text "E:/altera/13.0/PRJECT/HDB3/HDB3.v" 14 0 0 } } { "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { outv[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/altera/13.0/PRJECT/HDB3/" { { 0 { 0 ""} 0 36 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1631690604590 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "outv\[1\] " "Pin outv\[1\] not assigned to an exact location on the device" { } { { "e:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/altera/13.0/quartus/bin64/pin_planner.ppl" { outv[1] } } } { "HDB3.v" "" { Text "E:/altera/13.0/PRJECT/HDB3/HDB3.v" 14 0 0 } } { "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { outv[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/altera/13.0/PRJECT/HDB3/" { { 0 { 0 ""} 0 37 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1631690604590 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "outb\[0\] " "Pin outb\[0\] not assigned to an exact location on the device" { } { { "e:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/altera/13.0/quartus/bin64/pin_planner.ppl" { outb[0] } } } { "HDB3.v" "" { Text "E:/altera/13.0/PRJECT/HDB3/HDB3.v" 15 0 0 } } { "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { outb[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/altera/13.0/PRJECT/HDB3/" { { 0 { 0 ""} 0 38 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1631690604590 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "outb\[1\] " "Pin outb\[1\] not assigned to an exact location on the device" { } { { "e:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/altera/13.0/quartus/bin64/pin_planner.ppl" { outb[1] } } } { "HDB3.v" "" { Text "E:/altera/13.0/PRJECT/HDB3/HDB3.v" 15 0 0 } } { "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { outb[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/altera/13.0/PRJECT/HDB3/" { { 0 { 0 ""} 0 39 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1631690604590 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "outP " "Pin outP not assigned to an exact location on the device" { } { { "e:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/altera/13.0/quartus/bin64/pin_planner.ppl" { outP } } } { "HDB3.v" "" { Text "E:/altera/13.0/PRJECT/HDB3/HDB3.v" 16 0 0 } } { "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { outP } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/altera/13.0/PRJECT/HDB3/" { { 0 { 0 ""} 0 59 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1631690604590 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "outN " "Pin outN not assigned to an exact location on the device" { } { { "e:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/altera/13.0/quartus/bin64/pin_planner.ppl" { outN } } } { "HDB3.v" "" { Text "E:/altera/13.0/PRJECT/HDB3/HDB3.v" 16 0 0 } } { "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { outN } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/altera/13.0/PRJECT/HDB3/" { { 0 { 0 ""} 0 60 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1631690604590 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "outdata_P " "Pin outdata_P not assigned to an exact location on the device" { } { { "e:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/altera/13.0/quartus/bin64/pin_planner.ppl" { outdata_P } } } { "HDB3.v" "" { Text "E:/altera/13.0/PRJECT/HDB3/HDB3.v" 17 0 0 } } { "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { outdata_P } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/altera/13.0/PRJECT/HDB3/" { { 0 { 0 ""} 0 62 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1631690604590 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "outdata_N " "Pin outdata_N not assigned to an exact location on the device" { } { { "e:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/altera/13.0/quartus/bin64/pin_planner.ppl" { outdata_N } } } { "HDB3.v" "" { Text "E:/altera/13.0/PRJECT/HDB3/HDB3.v" 17 0 0 } } { "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { outdata_N } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/altera/13.0/PRJECT/HDB3/" { { 0 { 0 ""} 0 63 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1631690604590 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "outdata_v\[0\] " "Pin outdata_v\[0\] not assigned to an exact location on the device" { } { { "e:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/altera/13.0/quartus/bin64/pin_planner.ppl" { outdata_v[0] } } } { "HDB3.v" "" { Text "E:/altera/13.0/PRJECT/HDB3/HDB3.v" 18 0 0 } } { "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { outdata_v[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/altera/13.0/PRJECT/HDB3/" { { 0 { 0 ""} 0 48 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1631690604590 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "outdata_v\[1\] " "Pin outdata_v\[1\] not assigned to an exact location on the device" { } { { "e:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/altera/13.0/quartus/bin64/pin_planner.ppl" { outdata_v[1] } } } { "HDB3.v" "" { Text "E:/altera/13.0/PRJECT/HDB3/HDB3.v" 18 0 0 } } { "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { outdata_v[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/altera/13.0/PRJECT/HDB3/" { { 0 { 0 ""} 0 49 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1631690604590 ""} } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1631690604590 ""} { "Critical Warning" "WSTA_SDC_NOT_FOUND" "HDB3.sdc " "Synopsys Design Constraints File file not found: 'HDB3.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1631690604670 ""} { "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1631690604670 ""} { "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1631690604670 ""} { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk (placed in PIN 17 (CLK0, LVDSCLK0p, Input)) " "Automatically promoted node clk (placed in PIN 17 (CLK0, LVDSCLK0p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1631690604680 ""} } { { "e:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/altera/13.0/quartus/bin64/pin_planner.ppl" { clk } } } { "e:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "e:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "clk" } } } } { "HDB3.v" "" { Text "E:/altera/13.0/PRJECT/HDB3/HDB3.v" 9 0 0 } } { "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/altera/13.0/PRJECT/HDB3/" { { 0 { 0 ""} 0 51 9224 9983 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1631690604680 ""} { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "even_div16:div16\|clk_out " "Automatically promoted node even_div16:div16\|clk_out " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1631690604680 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "even_div16:div16\|clk_out~0 " "Destination node even_div16:div16\|clk_out~0" { } { { "even_div16.v" "" { Text "E:/altera/13.0/PRJECT/HDB3/even_div16.v" 3 -1 0 } } { "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { even_div16:div16|clk_out~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/altera/13.0/PRJECT/HDB3/" { { 0 { 0 ""} 0 167 9224 9983 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1631690604680 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "clk_16 " "Destination node clk_16" { } { { "e:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/altera/13.0/quartus/bin64/pin_planner.ppl" { clk_16 } } } { "e:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "e:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "clk_16" } } } } { "HDB3.v" "" { Text "E:/altera/13.0/PRJECT/HDB3/HDB3.v" 11 0 0 } } { "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk_16 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/altera/13.0/PRJECT/HDB3/" { { 0 { 0 ""} 0 53 9224 9983 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1631690604680 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1631690604680 ""} } { { "even_div16.v" "" { Text "E:/altera/13.0/PRJECT/HDB3/even_div16.v" 3 -1 0 } } { "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { even_div16:div16|clk_out } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/altera/13.0/PRJECT/HDB3/" { { 0 { 0 ""} 0 144 9224 9983 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1631690604680 ""} { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "even256_div:div256\|clk_out " "Automatically promoted node even256_div:div256\|clk_out " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1631690604680 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "even256_div:div256\|clk_out~0 " "Destination node even256_div:div256\|clk_out~0" { } { { "even256_div.v" "" { Text "E:/altera/13.0/PRJECT/HDB3/even256_div.v" 3 -1 0 } } { "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { even256_div:div256|clk_out~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/altera/13.0/PRJECT/HDB3/" { { 0 { 0 ""} 0 166 9224 9983 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1631690604680 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "clk_256 " "Destination node clk_256" { } { { "e:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/altera/13.0/quartus/bin64/pin_planner.ppl" { clk_256 } } } { "e:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "e:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "clk_256" } } } } { "HDB3.v" "" { Text "E:/altera/13.0/PRJECT/HDB3/HDB3.v" 11 0 0 } } { "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk_256 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/altera/13.0/PRJECT/HDB3/" { { 0 { 0 ""} 0 52 9224 9983 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1631690604680 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "clk_256_ad " "Destination node clk_256_ad" { } { { "e:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/altera/13.0/quartus/bin64/pin_planner.ppl" { clk_256_ad } } } { "e:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "e:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "clk_256_ad" } } } } { "HDB3.v" "" { Text "E:/altera/13.0/PRJECT/HDB3/HDB3.v" 11 0 0 } } { "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk_256_ad } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/altera/13.0/PRJECT/HDB3/" { { 0 { 0 ""} 0 55 9224 9983 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1631690604680 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "clk_256_da " "Destination node clk_256_da" { } { { "e:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/altera/13.0/quartus/bin64/pin_planner.ppl" { clk_256_da } } } { "HDB3.v" "" { Text "E:/altera/13.0/PRJECT/HDB3/HDB3.v" 11 0 0 } } { "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk_256_da } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/altera/13.0/PRJECT/HDB3/" { { 0 { 0 ""} 0 56 9224 9983 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1631690604680 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1631690604680 ""} } { { "even256_div.v" "" { Text "E:/altera/13.0/PRJECT/HDB3/even256_div.v" 3 -1 0 } } { "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { even256_div:div256|clk_out } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/altera/13.0/PRJECT/HDB3/" { { 0 { 0 ""} 0 154 9224 9983 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1631690604680 ""} { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "recover:u8\|clk_out " "Automatically promoted node recover:u8\|clk_out " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1631690604680 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "recover:u8\|clk_out~0 " "Destination node recover:u8\|clk_out~0" { } { { "recover.v" "" { Text "E:/altera/13.0/PRJECT/HDB3/recover.v" 6 -1 0 } } { "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { recover:u8|clk_out~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/altera/13.0/PRJECT/HDB3/" { { 0 { 0 ""} 0 169 9224 9983 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1631690604680 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "clk_recover " "Destination node clk_recover" { } { { "e:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/altera/13.0/quartus/bin64/pin_planner.ppl" { clk_recover } } } { "e:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "e:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "clk_recover" } } } } { "HDB3.v" "" { Text "E:/altera/13.0/PRJECT/HDB3/HDB3.v" 11 0 0 } } { "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk_recover } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/altera/13.0/PRJECT/HDB3/" { { 0 { 0 ""} 0 54 9224 9983 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1631690604680 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1631690604680 ""} } { { "recover.v" "" { Text "E:/altera/13.0/PRJECT/HDB3/recover.v" 6 -1 0 } } { "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { recover:u8|clk_out } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/altera/13.0/PRJECT/HDB3/" { { 0 { 0 ""} 0 95 9224 9983 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1631690604680 ""} { "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1631690604730 ""} { "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1631690604740 ""} { "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1631690604740 ""} { "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1631690604740 ""} { "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1631690604740 ""} { "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1631690604740 ""} { "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1631690604740 ""} { "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1631690604740 ""} { "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1631690604750 ""} { "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1631690604750 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1631690604750 ""} { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "11 unused 3.3V 0 11 0 " "Number of I/O pins in group: 11 (unused VREF, 3.3V VCCIO, 0 input, 11 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "I/O standards used: 3.3-V LVTTL." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1631690604750 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1631690604750 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1631690604750 ""} { "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 11 6 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 11 total pin(s) used -- 6 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1631690604750 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 3.3V 9 14 " "I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 9 total pin(s) used -- 14 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1631690604750 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use 3.3V 13 8 " "I/O bank number 3 does not use VREF pins and has 3.3V VCCIO pins. 13 total pin(s) used -- 8 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1631690604750 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use 3.3V 3 21 " "I/O bank number 4 does not use VREF pins and has 3.3V VCCIO pins. 3 total pin(s) used -- 21 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1631690604750 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1631690604750 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1631690604750 ""} { "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1631690604761 ""} { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1631690605041 ""} { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1631690605091 ""} { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1631690605101 ""} { "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1631690605488 ""} { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1631690605488 ""} { "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1631690605558 ""} { "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y0 X10_Y9 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y9" { } { { "loc" "" { Generic "E:/altera/13.0/PRJECT/HDB3/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y9"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y9"} 0 0 11 10 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1631690607048 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1631690607048 ""} { "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1631690607255 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1631690607255 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1631690607255 ""} { "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.48 " "Total time spent on timing analysis during the Fitter is 0.48 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1631690607265 ""} { "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1631690607265 ""} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "33 " "Found 33 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "clk_256 0 " "Pin \"clk_256\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1631690607265 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "clk_16 0 " "Pin \"clk_16\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1631690607265 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "clk_recover 0 " "Pin \"clk_recover\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1631690607265 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "clk_256_ad 0 " "Pin \"clk_256_ad\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1631690607265 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "clk_256_da 0 " "Pin \"clk_256_da\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1631690607265 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "data_out\[0\] 0 " "Pin \"data_out\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1631690607265 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "data_out\[1\] 0 " "Pin \"data_out\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1631690607265 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "data_out\[2\] 0 " "Pin \"data_out\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1631690607265 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "data_out\[3\] 0 " "Pin \"data_out\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1631690607265 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "data_out\[4\] 0 " "Pin \"data_out\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1631690607265 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "data_out\[5\] 0 " "Pin \"data_out\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1631690607265 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "data_out\[6\] 0 " "Pin \"data_out\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1631690607265 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "data_out\[7\] 0 " "Pin \"data_out\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1631690607265 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "outm 0 " "Pin \"outm\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1631690607265 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "outv\[0\] 0 " "Pin \"outv\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1631690607265 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "outv\[1\] 0 " "Pin \"outv\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1631690607265 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "outb\[0\] 0 " "Pin \"outb\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1631690607265 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "outb\[1\] 0 " "Pin \"outb\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1631690607265 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "outP 0 " "Pin \"outP\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1631690607265 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "outN 0 " "Pin \"outN\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1631690607265 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "data_out_check\[0\] 0 " "Pin \"data_out_check\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1631690607265 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "data_out_check\[1\] 0 " "Pin \"data_out_check\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1631690607265 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "data_out_check\[2\] 0 " "Pin \"data_out_check\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1631690607265 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "data_out_check\[3\] 0 " "Pin \"data_out_check\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1631690607265 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "data_out_check\[4\] 0 " "Pin \"data_out_check\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1631690607265 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "data_out_check\[5\] 0 " "Pin \"data_out_check\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1631690607265 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "data_out_check\[6\] 0 " "Pin \"data_out_check\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1631690607265 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "data_out_check\[7\] 0 " "Pin \"data_out_check\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1631690607265 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "finallyout 0 " "Pin \"finallyout\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1631690607265 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "outdata_P 0 " "Pin \"outdata_P\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1631690607265 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "outdata_N 0 " "Pin \"outdata_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1631690607265 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "outdata_v\[0\] 0 " "Pin \"outdata_v\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1631690607265 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "outdata_v\[1\] 0 " "Pin \"outdata_v\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1631690607265 ""} } { } 0 306006 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "Fitter" 0 -1 1631690607265 ""} { "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1631690607325 ""} { "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1631690607335 ""} { "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1631690607375 ""} { "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1631690607497 ""} { "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1631690607527 ""} { "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/altera/13.0/PRJECT/HDB3/output_files/HDB3.fit.smsg " "Generated suppressed messages file E:/altera/13.0/PRJECT/HDB3/output_files/HDB3.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1631690607577 ""} { "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5254 " "Peak virtual memory: 5254 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1631690607678 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 15 15:23:27 2021 " "Processing ended: Wed Sep 15 15:23:27 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1631690607678 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1631690607678 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1631690607678 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1631690607678 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1631690608631 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.0 Build 156 04/24/2013 SJ Full Version " "Version 13.0.0 Build 156 04/24/2013 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1631690608631 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 15 15:23:28 2021 " "Processing started: Wed Sep 15 15:23:28 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1631690608631 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1631690608631 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off HDB3 -c HDB3 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off HDB3 -c HDB3" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1631690608631 ""} { "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1631690609040 ""} { "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1631690609065 ""} { "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4567 " "Peak virtual memory: 4567 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1631690609255 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 15 15:23:29 2021 " "Processing ended: Wed Sep 15 15:23:29 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1631690609255 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1631690609255 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1631690609255 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1631690609255 ""} { "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1631690609828 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1631690610277 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.0 Build 156 04/24/2013 SJ Full Version " "Version 13.0.0 Build 156 04/24/2013 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1631690610277 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 15 15:23:29 2021 " "Processing started: Wed Sep 15 15:23:29 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1631690610277 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1631690610277 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta HDB3 -c HDB3 " "Command: quartus_sta HDB3 -c HDB3" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1631690610287 ""} { "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1631690610347 ""} { "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." { } { } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1631690610435 ""} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1631690610465 ""} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1631690610465 ""} { "Critical Warning" "WSTA_SDC_NOT_FOUND" "HDB3.sdc " "Synopsys Design Constraints File file not found: 'HDB3.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1631690610525 ""} { "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1631690610525 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name clk clk " "create_clock -period 1.000 -name clk clk" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1631690610525 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name even256_div:div256\|clk_out even256_div:div256\|clk_out " "create_clock -period 1.000 -name even256_div:div256\|clk_out even256_div:div256\|clk_out" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1631690610525 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name even_div16:div16\|clk_out even_div16:div16\|clk_out " "create_clock -period 1.000 -name even_div16:div16\|clk_out even_div16:div16\|clk_out" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1631690610525 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name recover:u8\|clk_out recover:u8\|clk_out " "create_clock -period 1.000 -name recover:u8\|clk_out recover:u8\|clk_out" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1631690610525 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1631690610525 ""} { "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1631690610525 ""} { "Info" "0" "" "Analyzing Slow Model" { } { } 0 0 "Analyzing Slow Model" 0 0 "Quartus II" 0 0 1631690610535 ""} { "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1631690610545 ""} { "Info" "ISTA_WORST_CASE_SLACK" "setup -2.148 " "Worst-case setup slack is -2.148" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631690610545 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631690610545 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.148 -19.036 clk " " -2.148 -19.036 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631690610545 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.642 -6.565 even256_div:div256\|clk_out " " -1.642 -6.565 even256_div:div256\|clk_out " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631690610545 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.588 -9.670 recover:u8\|clk_out " " -1.588 -9.670 recover:u8\|clk_out " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631690610545 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.509 -9.497 even_div16:div16\|clk_out " " -1.509 -9.497 even_div16:div16\|clk_out " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631690610545 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1631690610545 ""} { "Info" "ISTA_WORST_CASE_SLACK" "hold -2.972 " "Worst-case hold slack is -2.972" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631690610545 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631690610545 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.972 -5.944 even256_div:div256\|clk_out " " -2.972 -5.944 even256_div:div256\|clk_out " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631690610545 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.617 -2.617 clk " " -2.617 -2.617 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631690610545 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.499 0.000 even_div16:div16\|clk_out " " 0.499 0.000 even_div16:div16\|clk_out " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631690610545 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.499 0.000 recover:u8\|clk_out " " 0.499 0.000 recover:u8\|clk_out " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631690610545 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1631690610545 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1631690610555 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1631690610555 ""} { "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.941 " "Worst-case minimum pulse width slack is -1.941" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631690610555 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631690610555 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.941 -15.297 clk " " -1.941 -15.297 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631690610555 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.742 -41.552 even_div16:div16\|clk_out " " -0.742 -41.552 even_div16:div16\|clk_out " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631690610555 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.742 -22.260 even256_div:div256\|clk_out " " -0.742 -22.260 even256_div:div256\|clk_out " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631690610555 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.742 -19.292 recover:u8\|clk_out " " -0.742 -19.292 recover:u8\|clk_out " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631690610555 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1631690610555 ""} { "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1631690610625 ""} { "Info" "0" "" "Analyzing Fast Model" { } { } 0 0 "Analyzing Fast Model" 0 0 "Quartus II" 0 0 1631690610635 ""} { "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1631690610645 ""} { "Info" "ISTA_WORST_CASE_SLACK" "setup -0.075 " "Worst-case setup slack is -0.075" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631690610645 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631690610645 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.075 -0.600 clk " " -0.075 -0.600 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631690610645 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.058 0.000 recover:u8\|clk_out " " 0.058 0.000 recover:u8\|clk_out " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631690610645 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.164 0.000 even256_div:div256\|clk_out " " 0.164 0.000 even256_div:div256\|clk_out " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631690610645 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.212 0.000 even_div16:div16\|clk_out " " 0.212 0.000 even_div16:div16\|clk_out " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631690610645 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1631690610645 ""} { "Info" "ISTA_WORST_CASE_SLACK" "hold -1.389 " "Worst-case hold slack is -1.389" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631690610655 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631690610655 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.389 -1.389 clk " " -1.389 -1.389 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631690610655 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.350 -2.700 even256_div:div256\|clk_out " " -1.350 -2.700 even256_div:div256\|clk_out " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631690610655 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.215 0.000 even_div16:div16\|clk_out " " 0.215 0.000 even_div16:div16\|clk_out " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631690610655 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.215 0.000 recover:u8\|clk_out " " 0.215 0.000 recover:u8\|clk_out " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631690610655 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1631690610655 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1631690610655 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1631690610655 ""} { "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.380 " "Worst-case minimum pulse width slack is -1.380" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631690610665 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631690610665 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.380 -10.380 clk " " -1.380 -10.380 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631690610665 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.500 -28.000 even_div16:div16\|clk_out " " -0.500 -28.000 even_div16:div16\|clk_out " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631690610665 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.500 -15.000 even256_div:div256\|clk_out " " -0.500 -15.000 even256_div:div256\|clk_out " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631690610665 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.500 -13.000 recover:u8\|clk_out " " -0.500 -13.000 recover:u8\|clk_out " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631690610665 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1631690610665 ""} { "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1631690610745 ""} { "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1631690610775 ""} { "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1631690610775 ""} { "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 3 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4577 " "Peak virtual memory: 4577 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1631690610825 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 15 15:23:30 2021 " "Processing ended: Wed Sep 15 15:23:30 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1631690610825 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1631690610825 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1631690610825 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1631690610825 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1631690611811 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 64-Bit " "Running Quartus II 64-Bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.0 Build 156 04/24/2013 SJ Full Version " "Version 13.0.0 Build 156 04/24/2013 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1631690611811 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 15 15:23:31 2021 " "Processing started: Wed Sep 15 15:23:31 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1631690611811 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1631690611811 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off HDB3 -c HDB3 " "Command: quartus_eda --read_settings_files=off --write_settings_files=off HDB3 -c HDB3" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1631690611811 ""} { "Info" "IWSC_DONE_HDL_DUAL_SDO_GENERATION" "HDB3.vo\", \"HDB3_fast.vo HDB3_v.sdo HDB3_v_fast.sdo E:/altera/13.0/PRJECT/HDB3/simulation/modelsim/ simulation " "Generated files \"HDB3.vo\", \"HDB3_fast.vo\", \"HDB3_v.sdo\" and \"HDB3_v_fast.sdo\" in directory \"E:/altera/13.0/PRJECT/HDB3/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204026 "Generated files \"%1!s!\", \"%2!s!\" and \"%3!s!\" in directory \"%4!s!\" for EDA %5!s! tool" 0 0 "Quartus II" 0 -1 1631690612074 ""} { "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4524 " "Peak virtual memory: 4524 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1631690612104 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 15 15:23:32 2021 " "Processing ended: Wed Sep 15 15:23:32 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1631690612104 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1631690612104 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1631690612104 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1631690612104 ""} { "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 11 s " "Quartus II Full Compilation was successful. 0 errors, 11 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1631690612676 ""}