Foreword

Wanted to start this article with a comparison between
instruction sets of different CPUs/microcontrollers.

But for some reasons, I decided against it.
There already were enough boring "RISC versus CISC" debates.

And some of you may already have figured out, that the commercial
success of a specific CPU design isn't directly coupled to the
beauty/simplicity of its architecture.
It's hard/difficult to be honest/more_specific without instantly being
sued into a smoking crater.

So we better skip that part, and focus on MT15.
MT15 is a mostly transistorised CPU for architecture exploration,
but the concept described also could be used for building a 74xx
TTL CPU.

It appeared, that transistorised flipflops show a tendency to take
a lot of PCB space, so the decision was clear: to go with as few
flipflops as possible...
resulting in only a few CPU registers.

One of the simplest concepts of a CPU is an accumulator machine.
Means, there are two registers, visible to the "end user":

ACC: accumulator, basically a scratch_pad area.
Data calculation usually happens between ACC and memory,
the result is written back into ACC.

PC: program counter (also known as IP, instruction pointer)
points to the next instruction in program memory to be executed.
It usually is incremented after reading an instruction from memory.

Note, that there could also be two additional registers, not visible
to the "end user": temporary registers, holding data/address for
memory read/write cycles.

PDP8 is a nice example of such a design, but I decided for a
different approach.
Wanted to have a linear 64kWord address space, more addressing modes,
and the chance to increment/decrement/shift/clear a location in memory,
without changing the value in ACC (like with the 65C02).

Stack operations (push/pull) could be emulated by software,
using two instructions, one of them a "indirect move from/to memory",
while the other instruction increments/decrements the StackPointer
(a location in memory, pointing at the "top" of the stack).
Problem is, that those increments/decrements should not affect
the status register.

Decided for a write_back strategy as with PIC microcontrollers.
The ALU result from a data calculation between ACC/PC and memory
can be dropped (the "compare" instruction), written back to memory
(doesn't happen often), into ACC, or into PC.

Note, that writing into PC should be considered as "jump" or "branch",
causing to send program memory execution into a rather different direction.

To simplify implementation of conditional branches, the CPU is able
to execute or skip an instruction, depending on some Flags in the
status register.

Since we basically have some sort of accumulator machine,
most instructions would contain an OpCode and a parameter.
Thus, all MT15 instructions take two words of memory
(4 Bytes).

Here we go.

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